From 8e5427fbff71b1f20dd08d124ff3a4373b608f6e Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Mon, 28 Sep 2026 04:45:00 +0000 Subject: [PATCH] Tighten the clock period on designs with positive ws Signed-off-by: Matt Liberty --- flow/designs/asap7/aes-mbff/config.mk | 2 +- flow/designs/asap7/aes-mbff/constraint.sdc | 2 +- flow/designs/asap7/ibex/constraint.sdc | 2 +- flow/designs/asap7/mock-cpu/constraint.sdc | 4 ++-- flow/designs/gf180/uart-blocks/constraint.sdc | 2 +- flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc | 2 +- flow/designs/ihp-sg13g2/gcd/constraint.sdc | 2 +- flow/designs/ihp-sg13g2/jpeg/constraint.sdc | 2 +- flow/designs/nangate45/cva6/constraint.sdc | 2 +- flow/designs/sky130hd/ibex/constraint.sdc | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) diff --git a/flow/designs/asap7/aes-mbff/config.mk b/flow/designs/asap7/aes-mbff/config.mk index 1b99d55a65..ceb3d2cd72 100644 --- a/flow/designs/asap7/aes-mbff/config.mk +++ b/flow/designs/asap7/aes-mbff/config.mk @@ -7,7 +7,7 @@ export DESIGN_NICKNAME = aes-mbff export SYNTH_SLANG_ARGS += --ignore-timing export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes-mbff/constraint.sdc export ABC_AREA = 1 diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc index 09b55083d9..1505c5c0ec 100644 --- a/flow/designs/asap7/aes-mbff/constraint.sdc +++ b/flow/designs/asap7/aes-mbff/constraint.sdc @@ -1,6 +1,6 @@ set clk_name clk set clk_port_name clk -set clk_period 380 +set clk_period 350 # Match the old set_input/output_delay = 0.2 * clk_period budget, as # optimization targets only (no set_input/output_delay — see rationale in diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc index f99d7a0088..ce0b2b8dfe 100644 --- a/flow/designs/asap7/ibex/constraint.sdc +++ b/flow/designs/asap7/ibex/constraint.sdc @@ -1,6 +1,6 @@ set clk_name core_clock set clk_port_name clk_i -set clk_period 1000 +set clk_period 900 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/asap7/mock-cpu/constraint.sdc b/flow/designs/asap7/mock-cpu/constraint.sdc index 7cde9a6035..72d8abaa6b 100644 --- a/flow/designs/asap7/mock-cpu/constraint.sdc +++ b/flow/designs/asap7/mock-cpu/constraint.sdc @@ -31,8 +31,8 @@ source $::env(SDC_FILE_EXTRA) set sdc_version 2.0 -set clk_period 333 -set clk2_period 1000 +set clk_period 270 +set clk2_period 810 set clk1_name clk create_clock -name $clk1_name -period $clk_period \ diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc index dbceece162..57fce19f2a 100644 --- a/flow/designs/gf180/uart-blocks/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/constraint.sdc @@ -1,6 +1,6 @@ set clk_name clk set clk_port_name clk -set clk_period 6 +set clk_period 3.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc index 87b40db87f..3a88cfd2d9 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc @@ -1,6 +1,6 @@ set clk_name clk set clk_port_name clk -set clk_period 6 +set clk_period 3.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc index 98e03b4966..899d5ea28e 100644 --- a/flow/designs/ihp-sg13g2/gcd/constraint.sdc +++ b/flow/designs/ihp-sg13g2/gcd/constraint.sdc @@ -2,7 +2,7 @@ current_design gcd set clk_name core_clock set clk_port_name clk -set clk_period 2.8 +set clk_period 1.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc index ec75c33dd7..405a03d18b 100644 --- a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc +++ b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc @@ -2,7 +2,7 @@ current_design jpeg_encoder set clk_name clk set clk_port_name clk -set clk_period 8.0 +set clk_period 4.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/nangate45/cva6/constraint.sdc b/flow/designs/nangate45/cva6/constraint.sdc index ea6f22cc1a..209ec52b6e 100644 --- a/flow/designs/nangate45/cva6/constraint.sdc +++ b/flow/designs/nangate45/cva6/constraint.sdc @@ -3,7 +3,7 @@ set clk_name main_clk set clk_port clk_i set clk_ports_list [list $clk_port] -set clk_period 1000 +set clk_period 1.0 set input_delay 0.46 set output_delay 0.11 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc index b7ebd330aa..72bdf1d44d 100644 --- a/flow/designs/sky130hd/ibex/constraint.sdc +++ b/flow/designs/sky130hd/ibex/constraint.sdc @@ -2,7 +2,7 @@ current_design ibex_core set clk_name core_clock set clk_port_name clk_i -set clk_period 10.0 +set clk_period 8.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name]