From 12f3cfbfd0f4cded6fffc3e4afab0a2bf166514d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 29 Sep 2026 07:41:37 +0200 Subject: [PATCH] Remove REMOVE_ABC_BUFFERS support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit floorplan.tcl now always runs repair_timing_helper. The variable is dropped from variables.yaml, variables.json and FlowVariables.md. Designs are deliberately not touched here; they are handled by #4575, #4576, #4577, #4578 and #4579. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 2 -- flow/scripts/floorplan.tcl | 11 +++-------- flow/scripts/variables.json | 8 -------- flow/scripts/variables.yaml | 9 --------- 4 files changed, 3 insertions(+), 27 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 01afb784f3..d630594e52 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -246,7 +246,6 @@ configuration file. | PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | RCX_RULES| RC Extraction rules file path.| | | RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| -| REMOVE_ABC_BUFFERS (deprecated)| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| 0| | REMOVE_CELLS_FOR_LEC| String patterns directly passed to write_verilog -remove_cells <> for lec checks.| | | REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| @@ -431,7 +430,6 @@ configuration file. - [PRE_MACRO_PLACE_TCL](#PRE_MACRO_PLACE_TCL) - [PRE_PDN_TCL](#PRE_PDN_TCL) - [PRE_TAPCELL_TCL](#PRE_TAPCELL_TCL) -- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) - [RTLMP_AREA_WT](#RTLMP_AREA_WT) - [RTLMP_ARGS](#RTLMP_ARGS) diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index f4ca400139..bf503963cf 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -114,7 +114,7 @@ source_env_var_if_exists FOOTPRINT_TCL log_cmd set_dont_use $::env(DONT_USE_CELLS) # The transforms below (repair_tie_fanout, replace_arith_modules, -# remove_buffers, repair_timing_helper) look like synthesis-stage +# repair_timing_helper) look like synthesis-stage # operations: they all act on the netlist and don't touch placement. # But they DO depend on having a floorplan in place — initialize_floorplan # above placed the bterms on the die boundary and set_routing_layers @@ -151,13 +151,8 @@ if { [env_var_equals SWAP_ARITH_OPERATORS 1] } { log_cmd replace_arith_modules } -if { $::env(REMOVE_ABC_BUFFERS) } { - # remove buffers inserted by yosys/abc - log_cmd remove_buffers -} else { - # Skip clone & split - repair_timing_helper -setup -skip_last_gasp -sequence "unbuffer,sizeup,swap,vt_swap" -} +# Skip clone & split +repair_timing_helper -setup -skip_last_gasp -sequence "unbuffer,sizeup,swap,vt_swap" puts "Default units for flow" report_units diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 1e3d6d01ab..ecb6a4f3eb 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -938,14 +938,6 @@ "default": 0, "description": "Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].\n" }, - "REMOVE_ABC_BUFFERS": { - "default": 0, - "deprecated": 1, - "description": "Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.\n", - "stages": [ - "floorplan" - ] - }, "REMOVE_CELLS_FOR_LEC": { "description": "String patterns directly passed to write_verilog -remove_cells <> for lec checks.\n", "type": "string" diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 3c48319451..d7a142e321 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -507,15 +507,6 @@ BUFFER_PORTS_ARGS: Specify arguments to the buffer_ports call during placement. Only used if DONT_BUFFER_PORTS=0. stages: - place -REMOVE_ABC_BUFFERS: - description: > - Remove abc buffers from the netlist. If timing repair in floorplanning is - taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early - instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1. - stages: - - floorplan - deprecated: 1 - default: 0 BALANCE_ROWS: description: | Balance rows during placement.