diff --git a/README.md b/README.md index 177c240986..3c63043826 100644 --- a/README.md +++ b/README.md @@ -125,13 +125,6 @@ To build from your own git repository: cd /home/me/myproject make --file=~/OpenROAD-flow-scripts/flow/Makefile DESIGN_CONFIG=somefolder/config.mk ... -## Running a quick smoke-test of ORFS on your own Verilog - -You can [run ORFS on your own Verilog files](./flow/designs/asap7/minimal/README.md) -without setting up a project or moving your Verilog files and even learn -a thing or two about floorplan, placement and routing -before you create an .sdc file and a config.mk file. - ## Citing this Work If you use this software in any published work, we would appreciate a citation! diff --git a/docs/user/LargeDesigns.md b/docs/user/LargeDesigns.md index cb77b86fb4..0b9459b90b 100644 --- a/docs/user/LargeDesigns.md +++ b/docs/user/LargeDesigns.md @@ -6,18 +6,11 @@ ORFS has a `SYNTH_MEMORY_MAX_BITS` that limits the size of inferred memories tha Behavioral models of memories are used in simulation and FPGA tools oftentimes automatically combine hard memory macros with some extra logic to match the behavioral model. OpenROAD does not do such automatic memory inference and matching against real memories or fakemem. -## Doing a screening build +## Finding memories translated to flip flops -Before deciding how to set up a flow, it is useful to do a "screening build". All we're intersted in here is to know which modules we have and their relative sizes. This can help us identify memories that have not been successfully inferred by Yosys, which will manifest itself as very long synthesis times and appear in the OpenROAD hierarchical view with a large number of instances. - -The [minimal build configuration](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/asap7/minimal/README.md) - can be useful to do a screening build. - -Options useful for a screening build are, check out [config.mk](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/asap7/minimal/config.mk): - -- `SYNTH_HIERARCHICAL=1` and `SYNTH_MINIMUM_KEEP_SIZE=0`, to see all modules in the hierarchical OpenROAD view - `SYNTH_MEMORY_MAX_BITS=1024`, set a low threshold initially to get an error with list of memories in the system that will need to be dealt with in some way - `SYNTH_MOCK_LARGE_MEMORIES=1` enabled after first seeing the error report with memories. This sets the number of rows in memories larger than `SYNTH_MEMORY_MAX_BITS` to 1, so that synthesis will complete. +- `SYNTH_HIERARCHICAL=1` and `SYNTH_MINIMUM_KEEP_SIZE=0`, to see all modules in the hierarchical OpenROAD view and spot modules with an unexpectedly large number of instances ## Next steps on memories diff --git a/flow/designs/asap7/minimal/README.md b/flow/designs/asap7/minimal/README.md deleted file mode 100644 index bd8a2605c1..0000000000 --- a/flow/designs/asap7/minimal/README.md +++ /dev/null @@ -1,133 +0,0 @@ -# Report on a design prior to setting up a configuration - -This configuration allows running synthesis and floorplan -to extract some basic information useful when setting -up a config.mk file from scratch. - -Below, instructions are given to run synthesis, floorplan, placement and -global route, then examine the results in the GUI to see what a -realistic floorplan and settings might be for your Verilog files. - -The example below uses the designs/src/aes/*.v Verilog files, but -the Verilog files do not have to be located in the OpenROAD-flow-scripts -git repository, adjust the VERILOG_FILES argument to point to your Verilog -files: - -1. Clean and run flow through synthesis - ``` - make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_all synth do-1_3_synth - ``` -2. Bring up GUI for synthesis. - ``` - make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" gui_synth - ``` - -Where, the exploratory config.mk file to be replaced -by a design specific config.mk file is: - -``` -DESIGN_CONFIG=designs/asap7/minimal/config.mk -``` - -Verilog files that to be investigated are specified by: - -``` -VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" -``` - -The Verilog top module name is specified by: - -``` -DESIGN_NAME=aes_cipher_top -``` - -The entire flow is cleaned and synthesis re-run by: - -``` -clean_all synth do-1_3_synth -``` - -`do-1_3_synth` is an unconditional(no dependencies) make target that converts the synthesis Verilog netlist to an .odb file so that the `gui_synth` target is available to view the synthesis result in the OpenROAD GUI. The `gui_...` targets are created dynamically based on the existence of the corresponding .odb files, which is why you can get an error message if you specify `gui_...` on a make command line when the .odb file doesn't exist, even if your command is building the .odb file. - -The GUI is opened by the makefile target: - -``` -gui_synth -``` - -## `make gui_synth` OpenROAD GUI information - -![Alt text](gui_synth.png) - -The module hierarchy can here be examined to give a sense of -area required for the default placement density. - -## `make gui_yosys` OpenROAD GUI information for Yosys netlist - -It is possible to set up hierarchical synthesis using ORFS, in which case it can be helpful to view a netlist with blackboxed submodules, in which case there's no .odb file and `make gui_synth` is not available. - -## `make gui_floorplan` OpenROAD GUI information - -Next to iterate on floorplan settings: - -``` -make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_floorplan floorplan -``` - -``` -make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" gui_floorplan -``` - -A few more things can be learned from looking at this minimal floorplan: - -- Check that the floorplan size is not completely unreasonable and - at least there is a chance that this design could go through - placement with this density. - -![Alt text](gui_floorplan.png) - -## `make gui_place` OpenROAD GUI information - -Next to iterate on placement settings: - -``` -make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_place place -make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" gui_place -``` - -![Alt text](gui_place_heatmap.png) - -![Alt text](gui_place_module.png) - -From placement more information about how to set up the config.mk -file can be learned: - -- Examine estimated routing congestion to get a sense if there - is a chance that the design can be routed. -- Get a sense of size and location of modules -- The pins are on the edges and at least there - is enough space on the edges to fit the top level pins - -## CTS(Clock tree Synthesis) - -After placement, CTS (clock tree synthesis is run). However the minimal design does not have a clock, so CTS runs quickly, but does nothing. - -## `make gui_grt` OpenROAD GUI information - -For non-trivial designs, some more work will need to be done in floorplan and -placement before there is a chance that global routing will complete: - -``` -make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_grt grt -make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" gui_grt -``` - -![Alt text](gui_grt.png) - -Global routing congestion heatmap can be examined in the GUI. - -## Next steps - -Start creating a config.mk file for your design, write an .sdc file to -examine timing and find reasonable values for the CORE_UTILIZATION -and PLACE_DENSITY for your design considering routing congestion. diff --git a/flow/designs/asap7/minimal/config.mk b/flow/designs/asap7/minimal/config.mk deleted file mode 100644 index acc8d8fc1a..0000000000 --- a/flow/designs/asap7/minimal/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -export DESIGN_NICKNAME = minimal -export SDC_FILE ?= $(FLOW_HOME)/designs/asap7/minimal/empty.sdc -export PLATFORM = asap7 -# Faster build and more information in GUI with hierarchical synthesis -export SYNTH_HIERARCHICAL ?= 1 -# Keep all modules so we can examine the full hierarchy -export SYNTH_MINIMUM_KEEP_SIZE ?= 0 - -# Set the core utilization to 10% for the minimal design to -# maximize chances of getting an initial floorplan. This -# provides a generous area, yet not so big as to make making -# floorplan problematic -export CORE_UTILIZATION ?= 10 -# Low placement density to maximize chances of getting a floorplan -export PLACE_DENSITY ?= 0.20 - -# This won't work with an empty .sdc file -export SKIP_REPORT_METRICS ?= 1 - -# Faster build, remove these in your own config.mk -export SKIP_CTS_REPAIR_TIMING ?= 1 -export REMOVE_ABC_BUFFERS ?= 1 -export SKIP_INCREMENTAL_REPAIR ?= 1 -export GPL_TIMING_DRIVEN ?= 0 -export GPL_ROUTING_DRIVEN ?= 0 diff --git a/flow/designs/asap7/minimal/empty.sdc b/flow/designs/asap7/minimal/empty.sdc deleted file mode 100644 index 544afd58e7..0000000000 --- a/flow/designs/asap7/minimal/empty.sdc +++ /dev/null @@ -1,2 +0,0 @@ -# Creating a basic .sdc file is beyond the scope of -# simple configuration, much as writing Verilog is. diff --git a/flow/designs/asap7/minimal/gui_floorplan.png b/flow/designs/asap7/minimal/gui_floorplan.png deleted file mode 100644 index 59690cf85f..0000000000 Binary files a/flow/designs/asap7/minimal/gui_floorplan.png and /dev/null differ diff --git a/flow/designs/asap7/minimal/gui_grt.png b/flow/designs/asap7/minimal/gui_grt.png deleted file mode 100644 index 1f44d1d657..0000000000 Binary files a/flow/designs/asap7/minimal/gui_grt.png and /dev/null differ diff --git a/flow/designs/asap7/minimal/gui_place_heatmap.png b/flow/designs/asap7/minimal/gui_place_heatmap.png deleted file mode 100644 index d4c891ab3d..0000000000 Binary files a/flow/designs/asap7/minimal/gui_place_heatmap.png and /dev/null differ diff --git a/flow/designs/asap7/minimal/gui_place_module.png b/flow/designs/asap7/minimal/gui_place_module.png deleted file mode 100644 index 4ab4242b05..0000000000 Binary files a/flow/designs/asap7/minimal/gui_place_module.png and /dev/null differ diff --git a/flow/designs/asap7/minimal/gui_synth.png b/flow/designs/asap7/minimal/gui_synth.png deleted file mode 100644 index 54d8e821ef..0000000000 Binary files a/flow/designs/asap7/minimal/gui_synth.png and /dev/null differ diff --git a/flow/test/test_outoftree.sh b/flow/test/test_outoftree.sh deleted file mode 100755 index 884873470f..0000000000 --- a/flow/test/test_outoftree.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/usr/bin/env bash -# -# Out of tree integration smoke-test, run from ORFS/flow folder. -# -# Exit with error if anything is amiss, including evaluation of -# variable names such as $(false), unused variables, etc. -set -x -ue -o pipefail - -cd "$(dirname "$0")/.." -rm -rf results/outoftree/ -mkdir -p results/outoftree/ -cd results/outoftree/ -cp ../../designs/src/aes/* . -make --file=../../Makefile DESIGN_CONFIG=../../designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls *.v | xargs)" grt