diff --git a/designs/gt2n/bp_processor/BUILD.bazel b/designs/gt2n/bp_processor/BUILD.bazel new file mode 100644 index 00000000..04a18411 --- /dev/null +++ b/designs/gt2n/bp_processor/BUILD.bazel @@ -0,0 +1,16 @@ +package(default_visibility = ["//designs/gt2n/bp_processor:__subpackages__"]) + +filegroup( + name = "macros", + srcs = ["macros.v"], +) + +filegroup( + name = "sram_lefs", + srcs = glob(["sram/lef/*.lef"]), +) + +filegroup( + name = "sram_libs", + srcs = glob(["sram/lib/*.lib"]), +) diff --git a/designs/gt2n/bp_processor/bp_uno/BUILD.bazel b/designs/gt2n/bp_processor/bp_uno/BUILD.bazel new file mode 100644 index 00000000..7e62885e --- /dev/null +++ b/designs/gt2n/bp_processor/bp_uno/BUILD.bazel @@ -0,0 +1,33 @@ +load("//:defs.bzl", "hightide_design") +load("//designs/src/bp_processor:defs.bzl", "BP_COMMON_ARGS") + +_ARGS = dict(BP_COMMON_ARGS) + +_ARGS.update({ + # RTLMP auto macro placement, no hand-placed grid. + # Auto-sized via CORE_UTILIZATION rather than a fixed DIE_AREA/CORE_AREA. + "CORE_UTILIZATION": "35", + "PLACE_PINS_ARGS": "-min_distance 20 -min_distance_in_tracks", + "MACRO_PLACE_HALO": "8 8", + "PLACE_DENSITY": "0.42", + "MAX_ROUTING_LAYER": "M11", + "MIN_CLK_ROUTING_LAYER": "M4", + "TNS_END_PERCENT": "100", + "NUM_CORES": "16", +}) + +hightide_design( + name = "bp_processor", + platform = "gt2n", + verilog_files = [ + "//designs/src/bp_processor:rtl", + "//designs/gt2n/bp_processor:macros", + ], + sources = { + "SDC_FILE": [":constraint.sdc"], + "ADDITIONAL_LEFS": ["//designs/gt2n/bp_processor:sram_lefs"], + "ADDITIONAL_LIBS": ["//designs/gt2n/bp_processor:sram_libs"], + }, + arguments = _ARGS, + stage_data = {"synth": ["//designs/src/bp_processor:rtl_data"]}, +) diff --git a/designs/gt2n/bp_processor/bp_uno/constraint.sdc b/designs/gt2n/bp_processor/bp_uno/constraint.sdc new file mode 100644 index 00000000..7c498672 --- /dev/null +++ b/designs/gt2n/bp_processor/bp_uno/constraint.sdc @@ -0,0 +1,15 @@ +current_design bp_processor + +set clk_name CLK +set clk_port_name clk_i +set clk_period 4628 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/designs/gt2n/bp_processor/macros.v b/designs/gt2n/bp_processor/macros.v new file mode 100644 index 00000000..c3704e1e --- /dev/null +++ b/designs/gt2n/bp_processor/macros.v @@ -0,0 +1,235 @@ +// Auto-generated by designs/src/bp_processor/dev/gen_macros_v.py — do not edit. +// +// Large memories (listed below) bind to bsg_fakeram-generated +// fakeram_DxW_1rw macros via the rw0_* pin convention. Everything else +// falls through to a behavioural register array (synthesises to FFs). + +module bsg_mem_1rw_sync_synth ( + clk_i, + v_i, + reset_i, + data_i, + addr_i, + w_i, + data_o +); + parameter width_p = 0; + parameter els_p = 0; + parameter latch_last_read_p = 0; + parameter addr_width_lp = ((els_p == 1) || (els_p == 0) ? 1 : $clog2(els_p)); + parameter verbose_p = 1; + input clk_i; + input v_i; + input reset_i; + input [(width_p < 1 ? 0 : width_p - 1):0] data_i; + input [addr_width_lp - 1:0] addr_i; + input w_i; + output wire [(width_p < 1 ? 0 : width_p - 1):0] data_o; + wire unused = reset_i; + generate + if ((width_p == 0) || (els_p == 0)) begin : z + wire unused0 = &{clk_i, v_i, data_i, addr_i, w_i}; + assign data_o = 1'sb0; + end + else if ((els_p == 512) && (width_p == 64)) begin : fakeram_512x64 + fakeram_512x64_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in({64{w_i}}), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 64) && (width_p == 184)) begin : fakeram_64x184 + fakeram_64x184_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in({184{w_i}}), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 512) && (width_p == 8)) begin : fakeram_512x8 + fakeram_512x8_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in({8{w_i}}), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 64) && (width_p == 50)) begin : fakeram_64x50 + fakeram_64x50_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in({50{w_i}}), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 32) && (width_p == 48)) begin : fakeram_32x48 + fakeram_32x48_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in({48{w_i}}), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 128) && (width_p == 8)) begin : fakeram_128x8 + fakeram_128x8_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in({8{w_i}}), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else begin : nz + reg [addr_width_lp - 1:0] addr_r; + reg [width_p - 1:0] mem [els_p - 1:0]; + wire read_en; + wire [width_p - 1:0] data_out; + wire [addr_width_lp - 1:0] addr_li = (els_p > 0 ? addr_i : {addr_width_lp {1'sb0}}); + assign read_en = v_i & ~w_i; + assign data_out = mem[addr_r]; + always @(posedge clk_i) + if (read_en) + addr_r <= addr_li; + else + addr_r <= 1'sbx; + assign data_o = data_out; + always @(posedge clk_i) + if (v_i & w_i) + mem[addr_li] <= data_i; + end + endgenerate +endmodule + +module bsg_mem_1rw_sync_mask_write_bit_synth ( + clk_i, + reset_i, + data_i, + addr_i, + v_i, + w_mask_i, + w_i, + data_o +); + parameter width_p = 0; + parameter els_p = 0; + parameter latch_last_read_p = 0; + parameter addr_width_lp = ((els_p == 1) || (els_p == 0) ? 1 : $clog2(els_p)); + parameter verbose_p = 1; + input clk_i; + input reset_i; + input [(width_p < 1 ? 0 : width_p - 1):0] data_i; + input [addr_width_lp - 1:0] addr_i; + input v_i; + input [(width_p < 1 ? 0 : width_p - 1):0] w_mask_i; + input w_i; + output wire [(width_p < 1 ? 0 : width_p - 1):0] data_o; + wire unused = reset_i; + generate + if ((width_p == 0) || (els_p == 0)) begin : z + wire unused0 = &{clk_i, data_i, addr_i, v_i, w_mask_i, w_i}; + assign data_o = 1'sb0; + end + else if ((els_p == 512) && (width_p == 64)) begin : fakeram_512x64 + fakeram_512x64_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in(w_mask_i), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 64) && (width_p == 184)) begin : fakeram_64x184 + fakeram_64x184_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in(w_mask_i), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 512) && (width_p == 8)) begin : fakeram_512x8 + fakeram_512x8_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in(w_mask_i), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 64) && (width_p == 50)) begin : fakeram_64x50 + fakeram_64x50_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in(w_mask_i), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 32) && (width_p == 48)) begin : fakeram_32x48 + fakeram_32x48_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in(w_mask_i), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else if ((els_p == 128) && (width_p == 8)) begin : fakeram_128x8 + fakeram_128x8_1rw mem ( + .rw0_clk(clk_i), + .rw0_ce_in(v_i), + .rw0_we_in(w_i), + .rw0_wmask_in(w_mask_i), + .rw0_addr_in(addr_i), + .rw0_wd_in(data_i), + .rw0_rd_out(data_o) + ); + end + else begin : nz + reg [addr_width_lp - 1:0] addr_r; + reg [width_p - 1:0] mem [els_p - 1:0]; + wire read_en; + wire [width_p - 1:0] data_out; + wire [addr_width_lp - 1:0] addr_li = (els_p > 0 ? addr_i : {addr_width_lp {1'sb0}}); + assign read_en = v_i & ~w_i; + assign data_out = mem[addr_r]; + always @(posedge clk_i) + if (read_en) + addr_r <= addr_li; + else + addr_r <= 1'sbx; + assign data_o = data_out; + always @(posedge clk_i) + if (v_i & w_i) + mem[addr_li] <= data_i; + end + endgenerate +endmodule diff --git a/designs/gt2n/bp_processor/sram/lef/fakeram_128x8_1rw.lef b/designs/gt2n/bp_processor/sram/lef/fakeram_128x8_1rw.lef new file mode 100644 index 00000000..85c9e575 --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lef/fakeram_128x8_1rw.lef @@ -0,0 +1,390 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_128x8_1rw + FOREIGN fakeram_128x8_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 15.372 BY 9.648 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.290 0.036 1.302 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.336 0.138 15.372 0.150 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.336 1.290 15.372 1.302 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 9.606 0.175 9.648 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.505 9.606 1.519 9.648 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 9.606 2.863 9.648 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.193 9.606 4.207 9.648 ; + END + END rw0_wmask_in[7] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.442 0.036 2.454 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.594 0.036 3.606 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.336 2.442 15.372 2.454 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.336 3.594 15.372 3.606 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.037 0.000 2.051 0.042 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.913 0.000 3.927 0.042 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.789 0.000 5.803 0.042 ; + END + END rw0_wd_in[7] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.665 0.000 7.679 0.042 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.541 0.000 9.555 0.042 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.417 0.000 11.431 0.042 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.293 0.000 13.307 0.042 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 9.606 5.551 9.648 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 9.606 6.895 9.648 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 9.606 8.239 9.648 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 9.606 9.583 9.648 ; + END + END rw0_rd_out[7] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.746 0.036 4.758 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.898 0.036 5.910 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.050 0.036 7.062 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.202 0.036 8.214 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.336 4.746 15.372 4.758 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.336 5.898 15.372 5.910 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 15.336 7.050 15.372 7.062 ; + END + END rw0_addr_in[6] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 9.606 10.927 9.648 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.257 9.606 12.271 9.648 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 9.606 13.615 9.648 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 15.204 0.168 ; + RECT 0.168 0.504 15.204 0.552 ; + RECT 0.168 0.888 15.204 0.936 ; + RECT 0.168 1.272 15.204 1.320 ; + RECT 0.168 1.656 15.204 1.704 ; + RECT 0.168 2.040 15.204 2.088 ; + RECT 0.168 2.424 15.204 2.472 ; + RECT 0.168 2.808 15.204 2.856 ; + RECT 0.168 3.192 15.204 3.240 ; + RECT 0.168 3.576 15.204 3.624 ; + RECT 0.168 3.960 15.204 4.008 ; + RECT 0.168 4.344 15.204 4.392 ; + RECT 0.168 4.728 15.204 4.776 ; + RECT 0.168 5.112 15.204 5.160 ; + RECT 0.168 5.496 15.204 5.544 ; + RECT 0.168 5.880 15.204 5.928 ; + RECT 0.168 6.264 15.204 6.312 ; + RECT 0.168 6.648 15.204 6.696 ; + RECT 0.168 7.032 15.204 7.080 ; + RECT 0.168 7.416 15.204 7.464 ; + RECT 0.168 7.800 15.204 7.848 ; + RECT 0.168 8.184 15.204 8.232 ; + RECT 0.168 8.568 15.204 8.616 ; + RECT 0.168 8.952 15.204 9.000 ; + RECT 0.168 9.336 15.204 9.384 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.312 15.204 0.360 ; + RECT 0.168 0.696 15.204 0.744 ; + RECT 0.168 1.080 15.204 1.128 ; + RECT 0.168 1.464 15.204 1.512 ; + RECT 0.168 1.848 15.204 1.896 ; + RECT 0.168 2.232 15.204 2.280 ; + RECT 0.168 2.616 15.204 2.664 ; + RECT 0.168 3.000 15.204 3.048 ; + RECT 0.168 3.384 15.204 3.432 ; + RECT 0.168 3.768 15.204 3.816 ; + RECT 0.168 4.152 15.204 4.200 ; + RECT 0.168 4.536 15.204 4.584 ; + RECT 0.168 4.920 15.204 4.968 ; + RECT 0.168 5.304 15.204 5.352 ; + RECT 0.168 5.688 15.204 5.736 ; + RECT 0.168 6.072 15.204 6.120 ; + RECT 0.168 6.456 15.204 6.504 ; + RECT 0.168 6.840 15.204 6.888 ; + RECT 0.168 7.224 15.204 7.272 ; + RECT 0.168 7.608 15.204 7.656 ; + RECT 0.168 7.992 15.204 8.040 ; + RECT 0.168 8.376 15.204 8.424 ; + RECT 0.168 8.760 15.204 8.808 ; + RECT 0.168 9.144 15.204 9.192 ; + RECT 0.168 9.528 15.204 9.576 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 15.372 9.648 ; + LAYER M2 ; + RECT 0 0 15.372 9.648 ; + LAYER M3 ; + RECT 0 0 15.372 9.648 ; + LAYER M4 ; + RECT 0 0 15.372 9.648 ; + END +END fakeram_128x8_1rw + +END LIBRARY diff --git a/designs/gt2n/bp_processor/sram/lef/fakeram_32x48_1rw.lef b/designs/gt2n/bp_processor/sram/lef/fakeram_32x48_1rw.lef new file mode 100644 index 00000000..3e19f60b --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lef/fakeram_32x48_1rw.lef @@ -0,0 +1,1502 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_32x48_1rw + FOREIGN fakeram_32x48_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 11.508 BY 19.296 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.834 0.036 0.846 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.530 0.036 1.542 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.226 0.036 2.238 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.922 0.036 2.934 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.618 0.036 3.630 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.314 0.036 4.326 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.010 0.036 5.022 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.706 0.036 5.718 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.402 0.036 6.414 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.098 0.036 7.110 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.794 0.036 7.806 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 0.138 11.508 0.150 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 0.834 11.508 0.846 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 1.530 11.508 1.542 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 2.226 11.508 2.238 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 2.922 11.508 2.934 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 3.618 11.508 3.630 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 4.314 11.508 4.326 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 5.010 11.508 5.022 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 5.706 11.508 5.718 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 6.402 11.508 6.414 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 7.098 11.508 7.110 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 7.794 11.508 7.806 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 19.254 0.175 19.296 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.357 19.254 0.371 19.296 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.553 19.254 0.567 19.296 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.749 19.254 0.763 19.296 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.945 19.254 0.959 19.296 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.141 19.254 1.155 19.296 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.337 19.254 1.351 19.296 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.533 19.254 1.547 19.296 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.729 19.254 1.743 19.296 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.925 19.254 1.939 19.296 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.121 19.254 2.135 19.296 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.317 19.254 2.331 19.296 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.513 19.254 2.527 19.296 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.709 19.254 2.723 19.296 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.905 19.254 2.919 19.296 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.101 19.254 3.115 19.296 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.297 19.254 3.311 19.296 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.493 19.254 3.507 19.296 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.689 19.254 3.703 19.296 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.885 19.254 3.899 19.296 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.081 19.254 4.095 19.296 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.277 19.254 4.291 19.296 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.473 19.254 4.487 19.296 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.669 19.254 4.683 19.296 ; + END + END rw0_wmask_in[47] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.490 0.036 8.502 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.186 0.036 9.198 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.882 0.036 9.894 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.578 0.036 10.590 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.274 0.036 11.286 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.970 0.036 11.982 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.666 0.036 12.678 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.362 0.036 13.374 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.058 0.036 14.070 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.754 0.036 14.766 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.450 0.036 15.462 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.146 0.036 16.158 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 8.490 11.508 8.502 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 9.186 11.508 9.198 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 9.882 11.508 9.894 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 10.578 11.508 10.590 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 11.274 11.508 11.286 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 11.970 11.508 11.982 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 12.666 11.508 12.678 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 13.362 11.508 13.374 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 14.058 11.508 14.070 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 14.754 11.508 14.766 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 15.450 11.508 15.462 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 16.146 11.508 16.158 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.385 0.000 0.399 0.042 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.609 0.000 0.623 0.042 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.833 0.000 0.847 0.042 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.057 0.000 1.071 0.042 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.281 0.000 1.295 0.042 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.505 0.000 1.519 0.042 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.729 0.000 1.743 0.042 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.953 0.000 1.967 0.042 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.177 0.000 2.191 0.042 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.401 0.000 2.415 0.042 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.625 0.000 2.639 0.042 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 0.000 2.863 0.042 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.073 0.000 3.087 0.042 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.297 0.000 3.311 0.042 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.521 0.000 3.535 0.042 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.745 0.000 3.759 0.042 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.969 0.000 3.983 0.042 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.193 0.000 4.207 0.042 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.417 0.000 4.431 0.042 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.641 0.000 4.655 0.042 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.865 0.000 4.879 0.042 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.089 0.000 5.103 0.042 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.313 0.000 5.327 0.042 ; + END + END rw0_wd_in[47] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 0.000 5.551 0.042 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.985 0.000 5.999 0.042 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.209 0.000 6.223 0.042 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.433 0.000 6.447 0.042 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.657 0.000 6.671 0.042 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 0.000 6.895 0.042 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.105 0.000 7.119 0.042 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.329 0.000 7.343 0.042 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.553 0.000 7.567 0.042 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.777 0.000 7.791 0.042 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.001 0.000 8.015 0.042 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 0.000 8.239 0.042 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.449 0.000 8.463 0.042 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.673 0.000 8.687 0.042 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.897 0.000 8.911 0.042 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.121 0.000 9.135 0.042 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.345 0.000 9.359 0.042 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 0.000 9.583 0.042 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.793 0.000 9.807 0.042 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.017 0.000 10.031 0.042 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.241 0.000 10.255 0.042 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.465 0.000 10.479 0.042 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.689 0.000 10.703 0.042 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.865 19.254 4.879 19.296 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.061 19.254 5.075 19.296 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.257 19.254 5.271 19.296 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.453 19.254 5.467 19.296 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.649 19.254 5.663 19.296 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.845 19.254 5.859 19.296 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.041 19.254 6.055 19.296 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.237 19.254 6.251 19.296 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.433 19.254 6.447 19.296 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.629 19.254 6.643 19.296 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.825 19.254 6.839 19.296 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.021 19.254 7.035 19.296 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.217 19.254 7.231 19.296 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.413 19.254 7.427 19.296 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.609 19.254 7.623 19.296 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.805 19.254 7.819 19.296 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.001 19.254 8.015 19.296 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.197 19.254 8.211 19.296 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.393 19.254 8.407 19.296 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.589 19.254 8.603 19.296 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.785 19.254 8.799 19.296 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.981 19.254 8.995 19.296 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.177 19.254 9.191 19.296 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.373 19.254 9.387 19.296 ; + END + END rw0_rd_out[47] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.842 0.036 16.854 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.538 0.036 17.550 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.234 0.036 18.246 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 16.842 11.508 16.854 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 11.472 17.538 11.508 17.550 ; + END + END rw0_addr_in[4] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 19.254 9.583 19.296 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.765 19.254 9.779 19.296 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.961 19.254 9.975 19.296 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 11.340 0.168 ; + RECT 0.168 0.504 11.340 0.552 ; + RECT 0.168 0.888 11.340 0.936 ; + RECT 0.168 1.272 11.340 1.320 ; + RECT 0.168 1.656 11.340 1.704 ; + RECT 0.168 2.040 11.340 2.088 ; + RECT 0.168 2.424 11.340 2.472 ; + RECT 0.168 2.808 11.340 2.856 ; + RECT 0.168 3.192 11.340 3.240 ; + RECT 0.168 3.576 11.340 3.624 ; + RECT 0.168 3.960 11.340 4.008 ; + RECT 0.168 4.344 11.340 4.392 ; + RECT 0.168 4.728 11.340 4.776 ; + RECT 0.168 5.112 11.340 5.160 ; + RECT 0.168 5.496 11.340 5.544 ; + RECT 0.168 5.880 11.340 5.928 ; + RECT 0.168 6.264 11.340 6.312 ; + RECT 0.168 6.648 11.340 6.696 ; + RECT 0.168 7.032 11.340 7.080 ; + RECT 0.168 7.416 11.340 7.464 ; + RECT 0.168 7.800 11.340 7.848 ; + RECT 0.168 8.184 11.340 8.232 ; + RECT 0.168 8.568 11.340 8.616 ; + RECT 0.168 8.952 11.340 9.000 ; + RECT 0.168 9.336 11.340 9.384 ; + RECT 0.168 9.720 11.340 9.768 ; + RECT 0.168 10.104 11.340 10.152 ; + RECT 0.168 10.488 11.340 10.536 ; + RECT 0.168 10.872 11.340 10.920 ; + RECT 0.168 11.256 11.340 11.304 ; + RECT 0.168 11.640 11.340 11.688 ; + RECT 0.168 12.024 11.340 12.072 ; + RECT 0.168 12.408 11.340 12.456 ; + RECT 0.168 12.792 11.340 12.840 ; + RECT 0.168 13.176 11.340 13.224 ; + RECT 0.168 13.560 11.340 13.608 ; + RECT 0.168 13.944 11.340 13.992 ; + RECT 0.168 14.328 11.340 14.376 ; + RECT 0.168 14.712 11.340 14.760 ; + RECT 0.168 15.096 11.340 15.144 ; + RECT 0.168 15.480 11.340 15.528 ; + RECT 0.168 15.864 11.340 15.912 ; + RECT 0.168 16.248 11.340 16.296 ; + RECT 0.168 16.632 11.340 16.680 ; + RECT 0.168 17.016 11.340 17.064 ; + RECT 0.168 17.400 11.340 17.448 ; + RECT 0.168 17.784 11.340 17.832 ; + RECT 0.168 18.168 11.340 18.216 ; + RECT 0.168 18.552 11.340 18.600 ; + RECT 0.168 18.936 11.340 18.984 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.312 11.340 0.360 ; + RECT 0.168 0.696 11.340 0.744 ; + RECT 0.168 1.080 11.340 1.128 ; + RECT 0.168 1.464 11.340 1.512 ; + RECT 0.168 1.848 11.340 1.896 ; + RECT 0.168 2.232 11.340 2.280 ; + RECT 0.168 2.616 11.340 2.664 ; + RECT 0.168 3.000 11.340 3.048 ; + RECT 0.168 3.384 11.340 3.432 ; + RECT 0.168 3.768 11.340 3.816 ; + RECT 0.168 4.152 11.340 4.200 ; + RECT 0.168 4.536 11.340 4.584 ; + RECT 0.168 4.920 11.340 4.968 ; + RECT 0.168 5.304 11.340 5.352 ; + RECT 0.168 5.688 11.340 5.736 ; + RECT 0.168 6.072 11.340 6.120 ; + RECT 0.168 6.456 11.340 6.504 ; + RECT 0.168 6.840 11.340 6.888 ; + RECT 0.168 7.224 11.340 7.272 ; + RECT 0.168 7.608 11.340 7.656 ; + RECT 0.168 7.992 11.340 8.040 ; + RECT 0.168 8.376 11.340 8.424 ; + RECT 0.168 8.760 11.340 8.808 ; + RECT 0.168 9.144 11.340 9.192 ; + RECT 0.168 9.528 11.340 9.576 ; + RECT 0.168 9.912 11.340 9.960 ; + RECT 0.168 10.296 11.340 10.344 ; + RECT 0.168 10.680 11.340 10.728 ; + RECT 0.168 11.064 11.340 11.112 ; + RECT 0.168 11.448 11.340 11.496 ; + RECT 0.168 11.832 11.340 11.880 ; + RECT 0.168 12.216 11.340 12.264 ; + RECT 0.168 12.600 11.340 12.648 ; + RECT 0.168 12.984 11.340 13.032 ; + RECT 0.168 13.368 11.340 13.416 ; + RECT 0.168 13.752 11.340 13.800 ; + RECT 0.168 14.136 11.340 14.184 ; + RECT 0.168 14.520 11.340 14.568 ; + RECT 0.168 14.904 11.340 14.952 ; + RECT 0.168 15.288 11.340 15.336 ; + RECT 0.168 15.672 11.340 15.720 ; + RECT 0.168 16.056 11.340 16.104 ; + RECT 0.168 16.440 11.340 16.488 ; + RECT 0.168 16.824 11.340 16.872 ; + RECT 0.168 17.208 11.340 17.256 ; + RECT 0.168 17.592 11.340 17.640 ; + RECT 0.168 17.976 11.340 18.024 ; + RECT 0.168 18.360 11.340 18.408 ; + RECT 0.168 18.744 11.340 18.792 ; + RECT 0.168 19.128 11.340 19.176 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 11.508 19.296 ; + LAYER M2 ; + RECT 0 0 11.508 19.296 ; + LAYER M3 ; + RECT 0 0 11.508 19.296 ; + LAYER M4 ; + RECT 0 0 11.508 19.296 ; + END +END fakeram_32x48_1rw + +END LIBRARY diff --git a/designs/gt2n/bp_processor/sram/lef/fakeram_512x64_1rw.lef b/designs/gt2n/bp_processor/sram/lef/fakeram_512x64_1rw.lef new file mode 100644 index 00000000..681707e1 --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lef/fakeram_512x64_1rw.lef @@ -0,0 +1,2269 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_512x64_1rw + FOREIGN fakeram_512x64_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 61.362 BY 76.752 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.202 0.036 2.214 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.266 0.036 4.278 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.330 0.036 6.342 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.394 0.036 8.406 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.458 0.036 10.470 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.522 0.036 12.534 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.586 0.036 14.598 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.650 0.036 16.662 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.714 0.036 18.726 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.778 0.036 20.790 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.842 0.036 22.854 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 24.906 0.036 24.918 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 26.970 0.036 26.982 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 29.034 0.036 29.046 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 31.098 0.036 31.110 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 0.138 61.362 0.150 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 2.202 61.362 2.214 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 4.266 61.362 4.278 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 6.330 61.362 6.342 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 8.394 61.362 8.406 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 10.458 61.362 10.470 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 12.522 61.362 12.534 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 14.586 61.362 14.598 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 16.650 61.362 16.662 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 18.714 61.362 18.726 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 20.778 61.362 20.790 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 22.842 61.362 22.854 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 24.906 61.362 24.918 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 26.970 61.362 26.982 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 29.034 61.362 29.046 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 31.098 61.362 31.110 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 76.710 0.175 76.752 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.057 76.710 1.071 76.752 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.953 76.710 1.967 76.752 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 76.710 2.863 76.752 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.745 76.710 3.759 76.752 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.641 76.710 4.655 76.752 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 76.710 5.551 76.752 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.433 76.710 6.447 76.752 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.329 76.710 7.343 76.752 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 76.710 8.239 76.752 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.121 76.710 9.135 76.752 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.017 76.710 10.031 76.752 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 76.710 10.927 76.752 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.809 76.710 11.823 76.752 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.705 76.710 12.719 76.752 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 76.710 13.615 76.752 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.497 76.710 14.511 76.752 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.393 76.710 15.407 76.752 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.289 76.710 16.303 76.752 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.185 76.710 17.199 76.752 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.081 76.710 18.095 76.752 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.977 76.710 18.991 76.752 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.873 76.710 19.887 76.752 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.769 76.710 20.783 76.752 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.665 76.710 21.679 76.752 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 76.710 22.575 76.752 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.457 76.710 23.471 76.752 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.353 76.710 24.367 76.752 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.249 76.710 25.263 76.752 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.145 76.710 26.159 76.752 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.041 76.710 27.055 76.752 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.937 76.710 27.951 76.752 ; + END + END rw0_wmask_in[63] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 33.162 0.036 33.174 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 35.226 0.036 35.238 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 37.290 0.036 37.302 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 39.354 0.036 39.366 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 41.418 0.036 41.430 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 43.482 0.036 43.494 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 45.546 0.036 45.558 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 47.610 0.036 47.622 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 49.674 0.036 49.686 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 51.738 0.036 51.750 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 53.802 0.036 53.814 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 55.866 0.036 55.878 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 57.930 0.036 57.942 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 59.994 0.036 60.006 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 62.058 0.036 62.070 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 64.122 0.036 64.134 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 33.162 61.362 33.174 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 35.226 61.362 35.238 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 37.290 61.362 37.302 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 39.354 61.362 39.366 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 41.418 61.362 41.430 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 43.482 61.362 43.494 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 45.546 61.362 45.558 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 47.610 61.362 47.622 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 49.674 61.362 49.686 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 51.738 61.362 51.750 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 53.802 61.362 53.814 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 55.866 61.362 55.878 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 57.930 61.362 57.942 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 59.994 61.362 60.006 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 62.058 61.362 62.070 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 64.122 61.362 64.134 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.113 0.000 1.127 0.042 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.065 0.000 2.079 0.042 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.017 0.000 3.031 0.042 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.969 0.000 3.983 0.042 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.921 0.000 4.935 0.042 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.873 0.000 5.887 0.042 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.825 0.000 6.839 0.042 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.777 0.000 7.791 0.042 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.729 0.000 8.743 0.042 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.681 0.000 9.695 0.042 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.633 0.000 10.647 0.042 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.585 0.000 11.599 0.042 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.537 0.000 12.551 0.042 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.489 0.000 13.503 0.042 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.441 0.000 14.455 0.042 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.393 0.000 15.407 0.042 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.345 0.000 16.359 0.042 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.297 0.000 17.311 0.042 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.249 0.000 18.263 0.042 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.201 0.000 19.215 0.042 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.153 0.000 20.167 0.042 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.105 0.000 21.119 0.042 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.057 0.000 22.071 0.042 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.009 0.000 23.023 0.042 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.961 0.000 23.975 0.042 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.913 0.000 24.927 0.042 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.865 0.000 25.879 0.042 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.817 0.000 26.831 0.042 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.769 0.000 27.783 0.042 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.721 0.000 28.735 0.042 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.673 0.000 29.687 0.042 ; + END + END rw0_wd_in[63] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.625 0.000 30.639 0.042 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.577 0.000 31.591 0.042 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.529 0.000 32.543 0.042 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.481 0.000 33.495 0.042 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.433 0.000 34.447 0.042 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.385 0.000 35.399 0.042 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.337 0.000 36.351 0.042 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.289 0.000 37.303 0.042 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.241 0.000 38.255 0.042 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.193 0.000 39.207 0.042 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.145 0.000 40.159 0.042 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.097 0.000 41.111 0.042 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.049 0.000 42.063 0.042 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.001 0.000 43.015 0.042 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.953 0.000 43.967 0.042 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.905 0.000 44.919 0.042 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.857 0.000 45.871 0.042 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.809 0.000 46.823 0.042 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.761 0.000 47.775 0.042 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.713 0.000 48.727 0.042 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.665 0.000 49.679 0.042 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.617 0.000 50.631 0.042 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.569 0.000 51.583 0.042 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.521 0.000 52.535 0.042 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.473 0.000 53.487 0.042 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.425 0.000 54.439 0.042 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.377 0.000 55.391 0.042 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.329 0.000 56.343 0.042 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.281 0.000 57.295 0.042 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.233 0.000 58.247 0.042 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.185 0.000 59.199 0.042 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.137 0.000 60.151 0.042 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.833 76.710 28.847 76.752 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.729 76.710 29.743 76.752 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.625 76.710 30.639 76.752 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.521 76.710 31.535 76.752 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.417 76.710 32.431 76.752 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.313 76.710 33.327 76.752 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.209 76.710 34.223 76.752 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.105 76.710 35.119 76.752 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.001 76.710 36.015 76.752 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.897 76.710 36.911 76.752 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.793 76.710 37.807 76.752 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.689 76.710 38.703 76.752 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.585 76.710 39.599 76.752 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.481 76.710 40.495 76.752 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.377 76.710 41.391 76.752 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.273 76.710 42.287 76.752 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.169 76.710 43.183 76.752 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.065 76.710 44.079 76.752 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.961 76.710 44.975 76.752 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.857 76.710 45.871 76.752 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.753 76.710 46.767 76.752 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.649 76.710 47.663 76.752 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.545 76.710 48.559 76.752 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.441 76.710 49.455 76.752 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.337 76.710 50.351 76.752 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.233 76.710 51.247 76.752 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.129 76.710 52.143 76.752 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.025 76.710 53.039 76.752 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.921 76.710 53.935 76.752 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.817 76.710 54.831 76.752 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.713 76.710 55.727 76.752 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.609 76.710 56.623 76.752 ; + END + END rw0_rd_out[63] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 66.186 0.036 66.198 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 68.250 0.036 68.262 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 70.314 0.036 70.326 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 72.378 0.036 72.390 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 74.442 0.036 74.454 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 66.186 61.362 66.198 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 68.250 61.362 68.262 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 70.314 61.362 70.326 ; + END + END rw0_addr_in[7] + PIN rw0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 61.326 72.378 61.362 72.390 ; + END + END rw0_addr_in[8] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.505 76.710 57.519 76.752 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.401 76.710 58.415 76.752 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.297 76.710 59.311 76.752 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 61.194 0.168 ; + RECT 0.168 0.504 61.194 0.552 ; + RECT 0.168 0.888 61.194 0.936 ; + RECT 0.168 1.272 61.194 1.320 ; + RECT 0.168 1.656 61.194 1.704 ; + RECT 0.168 2.040 61.194 2.088 ; + RECT 0.168 2.424 61.194 2.472 ; + RECT 0.168 2.808 61.194 2.856 ; + RECT 0.168 3.192 61.194 3.240 ; + RECT 0.168 3.576 61.194 3.624 ; + RECT 0.168 3.960 61.194 4.008 ; + RECT 0.168 4.344 61.194 4.392 ; + RECT 0.168 4.728 61.194 4.776 ; + RECT 0.168 5.112 61.194 5.160 ; + RECT 0.168 5.496 61.194 5.544 ; + RECT 0.168 5.880 61.194 5.928 ; + RECT 0.168 6.264 61.194 6.312 ; + RECT 0.168 6.648 61.194 6.696 ; + RECT 0.168 7.032 61.194 7.080 ; + RECT 0.168 7.416 61.194 7.464 ; + RECT 0.168 7.800 61.194 7.848 ; + RECT 0.168 8.184 61.194 8.232 ; + RECT 0.168 8.568 61.194 8.616 ; + RECT 0.168 8.952 61.194 9.000 ; + RECT 0.168 9.336 61.194 9.384 ; + RECT 0.168 9.720 61.194 9.768 ; + RECT 0.168 10.104 61.194 10.152 ; + RECT 0.168 10.488 61.194 10.536 ; + RECT 0.168 10.872 61.194 10.920 ; + RECT 0.168 11.256 61.194 11.304 ; + RECT 0.168 11.640 61.194 11.688 ; + RECT 0.168 12.024 61.194 12.072 ; + RECT 0.168 12.408 61.194 12.456 ; + RECT 0.168 12.792 61.194 12.840 ; + RECT 0.168 13.176 61.194 13.224 ; + RECT 0.168 13.560 61.194 13.608 ; + RECT 0.168 13.944 61.194 13.992 ; + RECT 0.168 14.328 61.194 14.376 ; + RECT 0.168 14.712 61.194 14.760 ; + RECT 0.168 15.096 61.194 15.144 ; + RECT 0.168 15.480 61.194 15.528 ; + RECT 0.168 15.864 61.194 15.912 ; + RECT 0.168 16.248 61.194 16.296 ; + RECT 0.168 16.632 61.194 16.680 ; + RECT 0.168 17.016 61.194 17.064 ; + RECT 0.168 17.400 61.194 17.448 ; + RECT 0.168 17.784 61.194 17.832 ; + RECT 0.168 18.168 61.194 18.216 ; + RECT 0.168 18.552 61.194 18.600 ; + RECT 0.168 18.936 61.194 18.984 ; + RECT 0.168 19.320 61.194 19.368 ; + RECT 0.168 19.704 61.194 19.752 ; + RECT 0.168 20.088 61.194 20.136 ; + RECT 0.168 20.472 61.194 20.520 ; + RECT 0.168 20.856 61.194 20.904 ; + RECT 0.168 21.240 61.194 21.288 ; + RECT 0.168 21.624 61.194 21.672 ; + RECT 0.168 22.008 61.194 22.056 ; + RECT 0.168 22.392 61.194 22.440 ; + RECT 0.168 22.776 61.194 22.824 ; + RECT 0.168 23.160 61.194 23.208 ; + RECT 0.168 23.544 61.194 23.592 ; + RECT 0.168 23.928 61.194 23.976 ; + RECT 0.168 24.312 61.194 24.360 ; + RECT 0.168 24.696 61.194 24.744 ; + RECT 0.168 25.080 61.194 25.128 ; + RECT 0.168 25.464 61.194 25.512 ; + RECT 0.168 25.848 61.194 25.896 ; + RECT 0.168 26.232 61.194 26.280 ; + RECT 0.168 26.616 61.194 26.664 ; + RECT 0.168 27.000 61.194 27.048 ; + RECT 0.168 27.384 61.194 27.432 ; + RECT 0.168 27.768 61.194 27.816 ; + RECT 0.168 28.152 61.194 28.200 ; + RECT 0.168 28.536 61.194 28.584 ; + RECT 0.168 28.920 61.194 28.968 ; + RECT 0.168 29.304 61.194 29.352 ; + RECT 0.168 29.688 61.194 29.736 ; + RECT 0.168 30.072 61.194 30.120 ; + RECT 0.168 30.456 61.194 30.504 ; + RECT 0.168 30.840 61.194 30.888 ; + RECT 0.168 31.224 61.194 31.272 ; + RECT 0.168 31.608 61.194 31.656 ; + RECT 0.168 31.992 61.194 32.040 ; + RECT 0.168 32.376 61.194 32.424 ; + RECT 0.168 32.760 61.194 32.808 ; + RECT 0.168 33.144 61.194 33.192 ; + RECT 0.168 33.528 61.194 33.576 ; + RECT 0.168 33.912 61.194 33.960 ; + RECT 0.168 34.296 61.194 34.344 ; + RECT 0.168 34.680 61.194 34.728 ; + RECT 0.168 35.064 61.194 35.112 ; + RECT 0.168 35.448 61.194 35.496 ; + RECT 0.168 35.832 61.194 35.880 ; + RECT 0.168 36.216 61.194 36.264 ; + RECT 0.168 36.600 61.194 36.648 ; + RECT 0.168 36.984 61.194 37.032 ; + RECT 0.168 37.368 61.194 37.416 ; + RECT 0.168 37.752 61.194 37.800 ; + RECT 0.168 38.136 61.194 38.184 ; + RECT 0.168 38.520 61.194 38.568 ; + RECT 0.168 38.904 61.194 38.952 ; + RECT 0.168 39.288 61.194 39.336 ; + RECT 0.168 39.672 61.194 39.720 ; + RECT 0.168 40.056 61.194 40.104 ; + RECT 0.168 40.440 61.194 40.488 ; + RECT 0.168 40.824 61.194 40.872 ; + RECT 0.168 41.208 61.194 41.256 ; + RECT 0.168 41.592 61.194 41.640 ; + RECT 0.168 41.976 61.194 42.024 ; + RECT 0.168 42.360 61.194 42.408 ; + RECT 0.168 42.744 61.194 42.792 ; + RECT 0.168 43.128 61.194 43.176 ; + RECT 0.168 43.512 61.194 43.560 ; + RECT 0.168 43.896 61.194 43.944 ; + RECT 0.168 44.280 61.194 44.328 ; + RECT 0.168 44.664 61.194 44.712 ; + RECT 0.168 45.048 61.194 45.096 ; + RECT 0.168 45.432 61.194 45.480 ; + RECT 0.168 45.816 61.194 45.864 ; + RECT 0.168 46.200 61.194 46.248 ; + RECT 0.168 46.584 61.194 46.632 ; + RECT 0.168 46.968 61.194 47.016 ; + RECT 0.168 47.352 61.194 47.400 ; + RECT 0.168 47.736 61.194 47.784 ; + RECT 0.168 48.120 61.194 48.168 ; + RECT 0.168 48.504 61.194 48.552 ; + RECT 0.168 48.888 61.194 48.936 ; + RECT 0.168 49.272 61.194 49.320 ; + RECT 0.168 49.656 61.194 49.704 ; + RECT 0.168 50.040 61.194 50.088 ; + RECT 0.168 50.424 61.194 50.472 ; + RECT 0.168 50.808 61.194 50.856 ; + RECT 0.168 51.192 61.194 51.240 ; + RECT 0.168 51.576 61.194 51.624 ; + RECT 0.168 51.960 61.194 52.008 ; + RECT 0.168 52.344 61.194 52.392 ; + RECT 0.168 52.728 61.194 52.776 ; + RECT 0.168 53.112 61.194 53.160 ; + RECT 0.168 53.496 61.194 53.544 ; + RECT 0.168 53.880 61.194 53.928 ; + RECT 0.168 54.264 61.194 54.312 ; + RECT 0.168 54.648 61.194 54.696 ; + RECT 0.168 55.032 61.194 55.080 ; + RECT 0.168 55.416 61.194 55.464 ; + RECT 0.168 55.800 61.194 55.848 ; + RECT 0.168 56.184 61.194 56.232 ; + RECT 0.168 56.568 61.194 56.616 ; + RECT 0.168 56.952 61.194 57.000 ; + RECT 0.168 57.336 61.194 57.384 ; + RECT 0.168 57.720 61.194 57.768 ; + RECT 0.168 58.104 61.194 58.152 ; + RECT 0.168 58.488 61.194 58.536 ; + RECT 0.168 58.872 61.194 58.920 ; + RECT 0.168 59.256 61.194 59.304 ; + RECT 0.168 59.640 61.194 59.688 ; + RECT 0.168 60.024 61.194 60.072 ; + RECT 0.168 60.408 61.194 60.456 ; + RECT 0.168 60.792 61.194 60.840 ; + RECT 0.168 61.176 61.194 61.224 ; + RECT 0.168 61.560 61.194 61.608 ; + RECT 0.168 61.944 61.194 61.992 ; + RECT 0.168 62.328 61.194 62.376 ; + RECT 0.168 62.712 61.194 62.760 ; + RECT 0.168 63.096 61.194 63.144 ; + RECT 0.168 63.480 61.194 63.528 ; + RECT 0.168 63.864 61.194 63.912 ; + RECT 0.168 64.248 61.194 64.296 ; + RECT 0.168 64.632 61.194 64.680 ; + RECT 0.168 65.016 61.194 65.064 ; + RECT 0.168 65.400 61.194 65.448 ; + RECT 0.168 65.784 61.194 65.832 ; + RECT 0.168 66.168 61.194 66.216 ; + RECT 0.168 66.552 61.194 66.600 ; + RECT 0.168 66.936 61.194 66.984 ; + RECT 0.168 67.320 61.194 67.368 ; + RECT 0.168 67.704 61.194 67.752 ; + RECT 0.168 68.088 61.194 68.136 ; + RECT 0.168 68.472 61.194 68.520 ; + RECT 0.168 68.856 61.194 68.904 ; + RECT 0.168 69.240 61.194 69.288 ; + RECT 0.168 69.624 61.194 69.672 ; + RECT 0.168 70.008 61.194 70.056 ; + RECT 0.168 70.392 61.194 70.440 ; + RECT 0.168 70.776 61.194 70.824 ; + RECT 0.168 71.160 61.194 71.208 ; + RECT 0.168 71.544 61.194 71.592 ; + RECT 0.168 71.928 61.194 71.976 ; + RECT 0.168 72.312 61.194 72.360 ; + RECT 0.168 72.696 61.194 72.744 ; + RECT 0.168 73.080 61.194 73.128 ; + RECT 0.168 73.464 61.194 73.512 ; + RECT 0.168 73.848 61.194 73.896 ; + RECT 0.168 74.232 61.194 74.280 ; + RECT 0.168 74.616 61.194 74.664 ; + RECT 0.168 75.000 61.194 75.048 ; + RECT 0.168 75.384 61.194 75.432 ; + RECT 0.168 75.768 61.194 75.816 ; + RECT 0.168 76.152 61.194 76.200 ; + RECT 0.168 76.536 61.194 76.584 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.312 61.194 0.360 ; + RECT 0.168 0.696 61.194 0.744 ; + RECT 0.168 1.080 61.194 1.128 ; + RECT 0.168 1.464 61.194 1.512 ; + RECT 0.168 1.848 61.194 1.896 ; + RECT 0.168 2.232 61.194 2.280 ; + RECT 0.168 2.616 61.194 2.664 ; + RECT 0.168 3.000 61.194 3.048 ; + RECT 0.168 3.384 61.194 3.432 ; + RECT 0.168 3.768 61.194 3.816 ; + RECT 0.168 4.152 61.194 4.200 ; + RECT 0.168 4.536 61.194 4.584 ; + RECT 0.168 4.920 61.194 4.968 ; + RECT 0.168 5.304 61.194 5.352 ; + RECT 0.168 5.688 61.194 5.736 ; + RECT 0.168 6.072 61.194 6.120 ; + RECT 0.168 6.456 61.194 6.504 ; + RECT 0.168 6.840 61.194 6.888 ; + RECT 0.168 7.224 61.194 7.272 ; + RECT 0.168 7.608 61.194 7.656 ; + RECT 0.168 7.992 61.194 8.040 ; + RECT 0.168 8.376 61.194 8.424 ; + RECT 0.168 8.760 61.194 8.808 ; + RECT 0.168 9.144 61.194 9.192 ; + RECT 0.168 9.528 61.194 9.576 ; + RECT 0.168 9.912 61.194 9.960 ; + RECT 0.168 10.296 61.194 10.344 ; + RECT 0.168 10.680 61.194 10.728 ; + RECT 0.168 11.064 61.194 11.112 ; + RECT 0.168 11.448 61.194 11.496 ; + RECT 0.168 11.832 61.194 11.880 ; + RECT 0.168 12.216 61.194 12.264 ; + RECT 0.168 12.600 61.194 12.648 ; + RECT 0.168 12.984 61.194 13.032 ; + RECT 0.168 13.368 61.194 13.416 ; + RECT 0.168 13.752 61.194 13.800 ; + RECT 0.168 14.136 61.194 14.184 ; + RECT 0.168 14.520 61.194 14.568 ; + RECT 0.168 14.904 61.194 14.952 ; + RECT 0.168 15.288 61.194 15.336 ; + RECT 0.168 15.672 61.194 15.720 ; + RECT 0.168 16.056 61.194 16.104 ; + RECT 0.168 16.440 61.194 16.488 ; + RECT 0.168 16.824 61.194 16.872 ; + RECT 0.168 17.208 61.194 17.256 ; + RECT 0.168 17.592 61.194 17.640 ; + RECT 0.168 17.976 61.194 18.024 ; + RECT 0.168 18.360 61.194 18.408 ; + RECT 0.168 18.744 61.194 18.792 ; + RECT 0.168 19.128 61.194 19.176 ; + RECT 0.168 19.512 61.194 19.560 ; + RECT 0.168 19.896 61.194 19.944 ; + RECT 0.168 20.280 61.194 20.328 ; + RECT 0.168 20.664 61.194 20.712 ; + RECT 0.168 21.048 61.194 21.096 ; + RECT 0.168 21.432 61.194 21.480 ; + RECT 0.168 21.816 61.194 21.864 ; + RECT 0.168 22.200 61.194 22.248 ; + RECT 0.168 22.584 61.194 22.632 ; + RECT 0.168 22.968 61.194 23.016 ; + RECT 0.168 23.352 61.194 23.400 ; + RECT 0.168 23.736 61.194 23.784 ; + RECT 0.168 24.120 61.194 24.168 ; + RECT 0.168 24.504 61.194 24.552 ; + RECT 0.168 24.888 61.194 24.936 ; + RECT 0.168 25.272 61.194 25.320 ; + RECT 0.168 25.656 61.194 25.704 ; + RECT 0.168 26.040 61.194 26.088 ; + RECT 0.168 26.424 61.194 26.472 ; + RECT 0.168 26.808 61.194 26.856 ; + RECT 0.168 27.192 61.194 27.240 ; + RECT 0.168 27.576 61.194 27.624 ; + RECT 0.168 27.960 61.194 28.008 ; + RECT 0.168 28.344 61.194 28.392 ; + RECT 0.168 28.728 61.194 28.776 ; + RECT 0.168 29.112 61.194 29.160 ; + RECT 0.168 29.496 61.194 29.544 ; + RECT 0.168 29.880 61.194 29.928 ; + RECT 0.168 30.264 61.194 30.312 ; + RECT 0.168 30.648 61.194 30.696 ; + RECT 0.168 31.032 61.194 31.080 ; + RECT 0.168 31.416 61.194 31.464 ; + RECT 0.168 31.800 61.194 31.848 ; + RECT 0.168 32.184 61.194 32.232 ; + RECT 0.168 32.568 61.194 32.616 ; + RECT 0.168 32.952 61.194 33.000 ; + RECT 0.168 33.336 61.194 33.384 ; + RECT 0.168 33.720 61.194 33.768 ; + RECT 0.168 34.104 61.194 34.152 ; + RECT 0.168 34.488 61.194 34.536 ; + RECT 0.168 34.872 61.194 34.920 ; + RECT 0.168 35.256 61.194 35.304 ; + RECT 0.168 35.640 61.194 35.688 ; + RECT 0.168 36.024 61.194 36.072 ; + RECT 0.168 36.408 61.194 36.456 ; + RECT 0.168 36.792 61.194 36.840 ; + RECT 0.168 37.176 61.194 37.224 ; + RECT 0.168 37.560 61.194 37.608 ; + RECT 0.168 37.944 61.194 37.992 ; + RECT 0.168 38.328 61.194 38.376 ; + RECT 0.168 38.712 61.194 38.760 ; + RECT 0.168 39.096 61.194 39.144 ; + RECT 0.168 39.480 61.194 39.528 ; + RECT 0.168 39.864 61.194 39.912 ; + RECT 0.168 40.248 61.194 40.296 ; + RECT 0.168 40.632 61.194 40.680 ; + RECT 0.168 41.016 61.194 41.064 ; + RECT 0.168 41.400 61.194 41.448 ; + RECT 0.168 41.784 61.194 41.832 ; + RECT 0.168 42.168 61.194 42.216 ; + RECT 0.168 42.552 61.194 42.600 ; + RECT 0.168 42.936 61.194 42.984 ; + RECT 0.168 43.320 61.194 43.368 ; + RECT 0.168 43.704 61.194 43.752 ; + RECT 0.168 44.088 61.194 44.136 ; + RECT 0.168 44.472 61.194 44.520 ; + RECT 0.168 44.856 61.194 44.904 ; + RECT 0.168 45.240 61.194 45.288 ; + RECT 0.168 45.624 61.194 45.672 ; + RECT 0.168 46.008 61.194 46.056 ; + RECT 0.168 46.392 61.194 46.440 ; + RECT 0.168 46.776 61.194 46.824 ; + RECT 0.168 47.160 61.194 47.208 ; + RECT 0.168 47.544 61.194 47.592 ; + RECT 0.168 47.928 61.194 47.976 ; + RECT 0.168 48.312 61.194 48.360 ; + RECT 0.168 48.696 61.194 48.744 ; + RECT 0.168 49.080 61.194 49.128 ; + RECT 0.168 49.464 61.194 49.512 ; + RECT 0.168 49.848 61.194 49.896 ; + RECT 0.168 50.232 61.194 50.280 ; + RECT 0.168 50.616 61.194 50.664 ; + RECT 0.168 51.000 61.194 51.048 ; + RECT 0.168 51.384 61.194 51.432 ; + RECT 0.168 51.768 61.194 51.816 ; + RECT 0.168 52.152 61.194 52.200 ; + RECT 0.168 52.536 61.194 52.584 ; + RECT 0.168 52.920 61.194 52.968 ; + RECT 0.168 53.304 61.194 53.352 ; + RECT 0.168 53.688 61.194 53.736 ; + RECT 0.168 54.072 61.194 54.120 ; + RECT 0.168 54.456 61.194 54.504 ; + RECT 0.168 54.840 61.194 54.888 ; + RECT 0.168 55.224 61.194 55.272 ; + RECT 0.168 55.608 61.194 55.656 ; + RECT 0.168 55.992 61.194 56.040 ; + RECT 0.168 56.376 61.194 56.424 ; + RECT 0.168 56.760 61.194 56.808 ; + RECT 0.168 57.144 61.194 57.192 ; + RECT 0.168 57.528 61.194 57.576 ; + RECT 0.168 57.912 61.194 57.960 ; + RECT 0.168 58.296 61.194 58.344 ; + RECT 0.168 58.680 61.194 58.728 ; + RECT 0.168 59.064 61.194 59.112 ; + RECT 0.168 59.448 61.194 59.496 ; + RECT 0.168 59.832 61.194 59.880 ; + RECT 0.168 60.216 61.194 60.264 ; + RECT 0.168 60.600 61.194 60.648 ; + RECT 0.168 60.984 61.194 61.032 ; + RECT 0.168 61.368 61.194 61.416 ; + RECT 0.168 61.752 61.194 61.800 ; + RECT 0.168 62.136 61.194 62.184 ; + RECT 0.168 62.520 61.194 62.568 ; + RECT 0.168 62.904 61.194 62.952 ; + RECT 0.168 63.288 61.194 63.336 ; + RECT 0.168 63.672 61.194 63.720 ; + RECT 0.168 64.056 61.194 64.104 ; + RECT 0.168 64.440 61.194 64.488 ; + RECT 0.168 64.824 61.194 64.872 ; + RECT 0.168 65.208 61.194 65.256 ; + RECT 0.168 65.592 61.194 65.640 ; + RECT 0.168 65.976 61.194 66.024 ; + RECT 0.168 66.360 61.194 66.408 ; + RECT 0.168 66.744 61.194 66.792 ; + RECT 0.168 67.128 61.194 67.176 ; + RECT 0.168 67.512 61.194 67.560 ; + RECT 0.168 67.896 61.194 67.944 ; + RECT 0.168 68.280 61.194 68.328 ; + RECT 0.168 68.664 61.194 68.712 ; + RECT 0.168 69.048 61.194 69.096 ; + RECT 0.168 69.432 61.194 69.480 ; + RECT 0.168 69.816 61.194 69.864 ; + RECT 0.168 70.200 61.194 70.248 ; + RECT 0.168 70.584 61.194 70.632 ; + RECT 0.168 70.968 61.194 71.016 ; + RECT 0.168 71.352 61.194 71.400 ; + RECT 0.168 71.736 61.194 71.784 ; + RECT 0.168 72.120 61.194 72.168 ; + RECT 0.168 72.504 61.194 72.552 ; + RECT 0.168 72.888 61.194 72.936 ; + RECT 0.168 73.272 61.194 73.320 ; + RECT 0.168 73.656 61.194 73.704 ; + RECT 0.168 74.040 61.194 74.088 ; + RECT 0.168 74.424 61.194 74.472 ; + RECT 0.168 74.808 61.194 74.856 ; + RECT 0.168 75.192 61.194 75.240 ; + RECT 0.168 75.576 61.194 75.624 ; + RECT 0.168 75.960 61.194 76.008 ; + RECT 0.168 76.344 61.194 76.392 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 61.362 76.752 ; + LAYER M2 ; + RECT 0 0 61.362 76.752 ; + LAYER M3 ; + RECT 0 0 61.362 76.752 ; + LAYER M4 ; + RECT 0 0 61.362 76.752 ; + END +END fakeram_512x64_1rw + +END LIBRARY diff --git a/designs/gt2n/bp_processor/sram/lef/fakeram_512x8_1rw.lef b/designs/gt2n/bp_processor/sram/lef/fakeram_512x8_1rw.lef new file mode 100644 index 00000000..cfd194fd --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lef/fakeram_512x8_1rw.lef @@ -0,0 +1,458 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_512x8_1rw + FOREIGN fakeram_512x8_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 30.702 BY 19.296 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.226 0.036 2.238 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 0.138 30.702 0.150 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 2.226 30.702 2.238 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 19.254 0.175 19.296 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.905 19.254 2.919 19.296 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.649 19.254 5.663 19.296 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.393 19.254 8.407 19.296 ; + END + END rw0_wmask_in[7] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.314 0.036 4.326 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.402 0.036 6.414 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 4.314 30.702 4.326 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 6.402 30.702 6.414 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.941 0.000 3.955 0.042 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.721 0.000 7.735 0.042 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.501 0.000 11.515 0.042 ; + END + END rw0_wd_in[7] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.281 0.000 15.295 0.042 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.061 0.000 19.075 0.042 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.841 0.000 22.855 0.042 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.621 0.000 26.635 0.042 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.137 19.254 11.151 19.296 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.881 19.254 13.895 19.296 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.625 19.254 16.639 19.296 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.369 19.254 19.383 19.296 ; + END + END rw0_rd_out[7] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.490 0.036 8.502 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.578 0.036 10.590 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.666 0.036 12.678 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.754 0.036 14.766 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.842 0.036 16.854 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 8.490 30.702 8.502 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 10.578 30.702 10.590 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 12.666 30.702 12.678 ; + END + END rw0_addr_in[7] + PIN rw0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 30.666 14.754 30.702 14.766 ; + END + END rw0_addr_in[8] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.113 19.254 22.127 19.296 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.857 19.254 24.871 19.296 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.601 19.254 27.615 19.296 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 30.534 0.168 ; + RECT 0.168 0.504 30.534 0.552 ; + RECT 0.168 0.888 30.534 0.936 ; + RECT 0.168 1.272 30.534 1.320 ; + RECT 0.168 1.656 30.534 1.704 ; + RECT 0.168 2.040 30.534 2.088 ; + RECT 0.168 2.424 30.534 2.472 ; + RECT 0.168 2.808 30.534 2.856 ; + RECT 0.168 3.192 30.534 3.240 ; + RECT 0.168 3.576 30.534 3.624 ; + RECT 0.168 3.960 30.534 4.008 ; + RECT 0.168 4.344 30.534 4.392 ; + RECT 0.168 4.728 30.534 4.776 ; + RECT 0.168 5.112 30.534 5.160 ; + RECT 0.168 5.496 30.534 5.544 ; + RECT 0.168 5.880 30.534 5.928 ; + RECT 0.168 6.264 30.534 6.312 ; + RECT 0.168 6.648 30.534 6.696 ; + RECT 0.168 7.032 30.534 7.080 ; + RECT 0.168 7.416 30.534 7.464 ; + RECT 0.168 7.800 30.534 7.848 ; + RECT 0.168 8.184 30.534 8.232 ; + RECT 0.168 8.568 30.534 8.616 ; + RECT 0.168 8.952 30.534 9.000 ; + RECT 0.168 9.336 30.534 9.384 ; + RECT 0.168 9.720 30.534 9.768 ; + RECT 0.168 10.104 30.534 10.152 ; + RECT 0.168 10.488 30.534 10.536 ; + RECT 0.168 10.872 30.534 10.920 ; + RECT 0.168 11.256 30.534 11.304 ; + RECT 0.168 11.640 30.534 11.688 ; + RECT 0.168 12.024 30.534 12.072 ; + RECT 0.168 12.408 30.534 12.456 ; + RECT 0.168 12.792 30.534 12.840 ; + RECT 0.168 13.176 30.534 13.224 ; + RECT 0.168 13.560 30.534 13.608 ; + RECT 0.168 13.944 30.534 13.992 ; + RECT 0.168 14.328 30.534 14.376 ; + RECT 0.168 14.712 30.534 14.760 ; + RECT 0.168 15.096 30.534 15.144 ; + RECT 0.168 15.480 30.534 15.528 ; + RECT 0.168 15.864 30.534 15.912 ; + RECT 0.168 16.248 30.534 16.296 ; + RECT 0.168 16.632 30.534 16.680 ; + RECT 0.168 17.016 30.534 17.064 ; + RECT 0.168 17.400 30.534 17.448 ; + RECT 0.168 17.784 30.534 17.832 ; + RECT 0.168 18.168 30.534 18.216 ; + RECT 0.168 18.552 30.534 18.600 ; + RECT 0.168 18.936 30.534 18.984 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.312 30.534 0.360 ; + RECT 0.168 0.696 30.534 0.744 ; + RECT 0.168 1.080 30.534 1.128 ; + RECT 0.168 1.464 30.534 1.512 ; + RECT 0.168 1.848 30.534 1.896 ; + RECT 0.168 2.232 30.534 2.280 ; + RECT 0.168 2.616 30.534 2.664 ; + RECT 0.168 3.000 30.534 3.048 ; + RECT 0.168 3.384 30.534 3.432 ; + RECT 0.168 3.768 30.534 3.816 ; + RECT 0.168 4.152 30.534 4.200 ; + RECT 0.168 4.536 30.534 4.584 ; + RECT 0.168 4.920 30.534 4.968 ; + RECT 0.168 5.304 30.534 5.352 ; + RECT 0.168 5.688 30.534 5.736 ; + RECT 0.168 6.072 30.534 6.120 ; + RECT 0.168 6.456 30.534 6.504 ; + RECT 0.168 6.840 30.534 6.888 ; + RECT 0.168 7.224 30.534 7.272 ; + RECT 0.168 7.608 30.534 7.656 ; + RECT 0.168 7.992 30.534 8.040 ; + RECT 0.168 8.376 30.534 8.424 ; + RECT 0.168 8.760 30.534 8.808 ; + RECT 0.168 9.144 30.534 9.192 ; + RECT 0.168 9.528 30.534 9.576 ; + RECT 0.168 9.912 30.534 9.960 ; + RECT 0.168 10.296 30.534 10.344 ; + RECT 0.168 10.680 30.534 10.728 ; + RECT 0.168 11.064 30.534 11.112 ; + RECT 0.168 11.448 30.534 11.496 ; + RECT 0.168 11.832 30.534 11.880 ; + RECT 0.168 12.216 30.534 12.264 ; + RECT 0.168 12.600 30.534 12.648 ; + RECT 0.168 12.984 30.534 13.032 ; + RECT 0.168 13.368 30.534 13.416 ; + RECT 0.168 13.752 30.534 13.800 ; + RECT 0.168 14.136 30.534 14.184 ; + RECT 0.168 14.520 30.534 14.568 ; + RECT 0.168 14.904 30.534 14.952 ; + RECT 0.168 15.288 30.534 15.336 ; + RECT 0.168 15.672 30.534 15.720 ; + RECT 0.168 16.056 30.534 16.104 ; + RECT 0.168 16.440 30.534 16.488 ; + RECT 0.168 16.824 30.534 16.872 ; + RECT 0.168 17.208 30.534 17.256 ; + RECT 0.168 17.592 30.534 17.640 ; + RECT 0.168 17.976 30.534 18.024 ; + RECT 0.168 18.360 30.534 18.408 ; + RECT 0.168 18.744 30.534 18.792 ; + RECT 0.168 19.128 30.534 19.176 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 30.702 19.296 ; + LAYER M2 ; + RECT 0 0 30.702 19.296 ; + LAYER M3 ; + RECT 0 0 30.702 19.296 ; + LAYER M4 ; + RECT 0 0 30.702 19.296 ; + END +END fakeram_512x8_1rw + +END LIBRARY diff --git a/designs/gt2n/bp_processor/sram/lef/fakeram_64x184_1rw.lef b/designs/gt2n/bp_processor/sram/lef/fakeram_64x184_1rw.lef new file mode 100644 index 00000000..1dcc1e52 --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lef/fakeram_64x184_1rw.lef @@ -0,0 +1,5283 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x184_1rw + FOREIGN fakeram_64x184_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 44.100 BY 38.448 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.522 0.036 0.534 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.906 0.036 0.918 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.290 0.036 1.302 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.674 0.036 1.686 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.058 0.036 2.070 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.442 0.036 2.454 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.826 0.036 2.838 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.210 0.036 3.222 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.594 0.036 3.606 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.978 0.036 3.990 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.362 0.036 4.374 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.746 0.036 4.758 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.130 0.036 5.142 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.514 0.036 5.526 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.898 0.036 5.910 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.282 0.036 6.294 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.666 0.036 6.678 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.050 0.036 7.062 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.434 0.036 7.446 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.818 0.036 7.830 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.202 0.036 8.214 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.586 0.036 8.598 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.970 0.036 8.982 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.354 0.036 9.366 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.738 0.036 9.750 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.122 0.036 10.134 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.506 0.036 10.518 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.890 0.036 10.902 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.274 0.036 11.286 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.658 0.036 11.670 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.042 0.036 12.054 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.426 0.036 12.438 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.810 0.036 12.822 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.194 0.036 13.206 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.578 0.036 13.590 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.962 0.036 13.974 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.346 0.036 14.358 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.730 0.036 14.742 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.114 0.036 15.126 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.498 0.036 15.510 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.882 0.036 15.894 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.266 0.036 16.278 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.650 0.036 16.662 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.034 0.036 17.046 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.418 0.036 17.430 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 0.138 44.100 0.150 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 0.522 44.100 0.534 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 0.906 44.100 0.918 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 1.290 44.100 1.302 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 1.674 44.100 1.686 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 2.058 44.100 2.070 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 2.442 44.100 2.454 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 2.826 44.100 2.838 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 3.210 44.100 3.222 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 3.594 44.100 3.606 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 3.978 44.100 3.990 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 4.362 44.100 4.374 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 4.746 44.100 4.758 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 5.130 44.100 5.142 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 5.514 44.100 5.526 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 5.898 44.100 5.910 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 6.282 44.100 6.294 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 6.666 44.100 6.678 ; + END + END rw0_wmask_in[63] + PIN rw0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 7.050 44.100 7.062 ; + END + END rw0_wmask_in[64] + PIN rw0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 7.434 44.100 7.446 ; + END + END rw0_wmask_in[65] + PIN rw0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 7.818 44.100 7.830 ; + END + END rw0_wmask_in[66] + PIN rw0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 8.202 44.100 8.214 ; + END + END rw0_wmask_in[67] + PIN rw0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 8.586 44.100 8.598 ; + END + END rw0_wmask_in[68] + PIN rw0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 8.970 44.100 8.982 ; + END + END rw0_wmask_in[69] + PIN rw0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 9.354 44.100 9.366 ; + END + END rw0_wmask_in[70] + PIN rw0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 9.738 44.100 9.750 ; + END + END rw0_wmask_in[71] + PIN rw0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 10.122 44.100 10.134 ; + END + END rw0_wmask_in[72] + PIN rw0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 10.506 44.100 10.518 ; + END + END rw0_wmask_in[73] + PIN rw0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 10.890 44.100 10.902 ; + END + END rw0_wmask_in[74] + PIN rw0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 11.274 44.100 11.286 ; + END + END rw0_wmask_in[75] + PIN rw0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 11.658 44.100 11.670 ; + END + END rw0_wmask_in[76] + PIN rw0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 12.042 44.100 12.054 ; + END + END rw0_wmask_in[77] + PIN rw0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 12.426 44.100 12.438 ; + END + END rw0_wmask_in[78] + PIN rw0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 12.810 44.100 12.822 ; + END + END rw0_wmask_in[79] + PIN rw0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 13.194 44.100 13.206 ; + END + END rw0_wmask_in[80] + PIN rw0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 13.578 44.100 13.590 ; + END + END rw0_wmask_in[81] + PIN rw0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 13.962 44.100 13.974 ; + END + END rw0_wmask_in[82] + PIN rw0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 14.346 44.100 14.358 ; + END + END rw0_wmask_in[83] + PIN rw0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 14.730 44.100 14.742 ; + END + END rw0_wmask_in[84] + PIN rw0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 15.114 44.100 15.126 ; + END + END rw0_wmask_in[85] + PIN rw0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 15.498 44.100 15.510 ; + END + END rw0_wmask_in[86] + PIN rw0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 15.882 44.100 15.894 ; + END + END rw0_wmask_in[87] + PIN rw0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 16.266 44.100 16.278 ; + END + END rw0_wmask_in[88] + PIN rw0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 16.650 44.100 16.662 ; + END + END rw0_wmask_in[89] + PIN rw0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 17.034 44.100 17.046 ; + END + END rw0_wmask_in[90] + PIN rw0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 17.418 44.100 17.430 ; + END + END rw0_wmask_in[91] + PIN rw0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 38.406 0.175 38.448 ; + END + END rw0_wmask_in[92] + PIN rw0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.385 38.406 0.399 38.448 ; + END + END rw0_wmask_in[93] + PIN rw0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.609 38.406 0.623 38.448 ; + END + END rw0_wmask_in[94] + PIN rw0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.833 38.406 0.847 38.448 ; + END + END rw0_wmask_in[95] + PIN rw0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.057 38.406 1.071 38.448 ; + END + END rw0_wmask_in[96] + PIN rw0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.281 38.406 1.295 38.448 ; + END + END rw0_wmask_in[97] + PIN rw0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.505 38.406 1.519 38.448 ; + END + END rw0_wmask_in[98] + PIN rw0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.729 38.406 1.743 38.448 ; + END + END rw0_wmask_in[99] + PIN rw0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.953 38.406 1.967 38.448 ; + END + END rw0_wmask_in[100] + PIN rw0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.177 38.406 2.191 38.448 ; + END + END rw0_wmask_in[101] + PIN rw0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.401 38.406 2.415 38.448 ; + END + END rw0_wmask_in[102] + PIN rw0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.625 38.406 2.639 38.448 ; + END + END rw0_wmask_in[103] + PIN rw0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 38.406 2.863 38.448 ; + END + END rw0_wmask_in[104] + PIN rw0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.073 38.406 3.087 38.448 ; + END + END rw0_wmask_in[105] + PIN rw0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.297 38.406 3.311 38.448 ; + END + END rw0_wmask_in[106] + PIN rw0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.521 38.406 3.535 38.448 ; + END + END rw0_wmask_in[107] + PIN rw0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.745 38.406 3.759 38.448 ; + END + END rw0_wmask_in[108] + PIN rw0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.969 38.406 3.983 38.448 ; + END + END rw0_wmask_in[109] + PIN rw0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.193 38.406 4.207 38.448 ; + END + END rw0_wmask_in[110] + PIN rw0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.417 38.406 4.431 38.448 ; + END + END rw0_wmask_in[111] + PIN rw0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.641 38.406 4.655 38.448 ; + END + END rw0_wmask_in[112] + PIN rw0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.865 38.406 4.879 38.448 ; + END + END rw0_wmask_in[113] + PIN rw0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.089 38.406 5.103 38.448 ; + END + END rw0_wmask_in[114] + PIN rw0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.313 38.406 5.327 38.448 ; + END + END rw0_wmask_in[115] + PIN rw0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 38.406 5.551 38.448 ; + END + END rw0_wmask_in[116] + PIN rw0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 38.406 5.775 38.448 ; + END + END rw0_wmask_in[117] + PIN rw0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.985 38.406 5.999 38.448 ; + END + END rw0_wmask_in[118] + PIN rw0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.209 38.406 6.223 38.448 ; + END + END rw0_wmask_in[119] + PIN rw0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.433 38.406 6.447 38.448 ; + END + END rw0_wmask_in[120] + PIN rw0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.657 38.406 6.671 38.448 ; + END + END rw0_wmask_in[121] + PIN rw0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 38.406 6.895 38.448 ; + END + END rw0_wmask_in[122] + PIN rw0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.105 38.406 7.119 38.448 ; + END + END rw0_wmask_in[123] + PIN rw0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.329 38.406 7.343 38.448 ; + END + END rw0_wmask_in[124] + PIN rw0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.553 38.406 7.567 38.448 ; + END + END rw0_wmask_in[125] + PIN rw0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.777 38.406 7.791 38.448 ; + END + END rw0_wmask_in[126] + PIN rw0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.001 38.406 8.015 38.448 ; + END + END rw0_wmask_in[127] + PIN rw0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 38.406 8.239 38.448 ; + END + END rw0_wmask_in[128] + PIN rw0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.449 38.406 8.463 38.448 ; + END + END rw0_wmask_in[129] + PIN rw0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.673 38.406 8.687 38.448 ; + END + END rw0_wmask_in[130] + PIN rw0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.897 38.406 8.911 38.448 ; + END + END rw0_wmask_in[131] + PIN rw0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.121 38.406 9.135 38.448 ; + END + END rw0_wmask_in[132] + PIN rw0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.345 38.406 9.359 38.448 ; + END + END rw0_wmask_in[133] + PIN rw0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 38.406 9.583 38.448 ; + END + END rw0_wmask_in[134] + PIN rw0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.793 38.406 9.807 38.448 ; + END + END rw0_wmask_in[135] + PIN rw0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.017 38.406 10.031 38.448 ; + END + END rw0_wmask_in[136] + PIN rw0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.241 38.406 10.255 38.448 ; + END + END rw0_wmask_in[137] + PIN rw0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.465 38.406 10.479 38.448 ; + END + END rw0_wmask_in[138] + PIN rw0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.689 38.406 10.703 38.448 ; + END + END rw0_wmask_in[139] + PIN rw0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 38.406 10.927 38.448 ; + END + END rw0_wmask_in[140] + PIN rw0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.137 38.406 11.151 38.448 ; + END + END rw0_wmask_in[141] + PIN rw0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 38.406 11.375 38.448 ; + END + END rw0_wmask_in[142] + PIN rw0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.585 38.406 11.599 38.448 ; + END + END rw0_wmask_in[143] + PIN rw0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.809 38.406 11.823 38.448 ; + END + END rw0_wmask_in[144] + PIN rw0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.033 38.406 12.047 38.448 ; + END + END rw0_wmask_in[145] + PIN rw0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.257 38.406 12.271 38.448 ; + END + END rw0_wmask_in[146] + PIN rw0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.481 38.406 12.495 38.448 ; + END + END rw0_wmask_in[147] + PIN rw0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.705 38.406 12.719 38.448 ; + END + END rw0_wmask_in[148] + PIN rw0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.929 38.406 12.943 38.448 ; + END + END rw0_wmask_in[149] + PIN rw0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.153 38.406 13.167 38.448 ; + END + END rw0_wmask_in[150] + PIN rw0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.377 38.406 13.391 38.448 ; + END + END rw0_wmask_in[151] + PIN rw0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 38.406 13.615 38.448 ; + END + END rw0_wmask_in[152] + PIN rw0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.825 38.406 13.839 38.448 ; + END + END rw0_wmask_in[153] + PIN rw0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.049 38.406 14.063 38.448 ; + END + END rw0_wmask_in[154] + PIN rw0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.273 38.406 14.287 38.448 ; + END + END rw0_wmask_in[155] + PIN rw0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.497 38.406 14.511 38.448 ; + END + END rw0_wmask_in[156] + PIN rw0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.721 38.406 14.735 38.448 ; + END + END rw0_wmask_in[157] + PIN rw0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.945 38.406 14.959 38.448 ; + END + END rw0_wmask_in[158] + PIN rw0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.169 38.406 15.183 38.448 ; + END + END rw0_wmask_in[159] + PIN rw0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.393 38.406 15.407 38.448 ; + END + END rw0_wmask_in[160] + PIN rw0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.617 38.406 15.631 38.448 ; + END + END rw0_wmask_in[161] + PIN rw0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.841 38.406 15.855 38.448 ; + END + END rw0_wmask_in[162] + PIN rw0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.065 38.406 16.079 38.448 ; + END + END rw0_wmask_in[163] + PIN rw0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.289 38.406 16.303 38.448 ; + END + END rw0_wmask_in[164] + PIN rw0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.513 38.406 16.527 38.448 ; + END + END rw0_wmask_in[165] + PIN rw0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.737 38.406 16.751 38.448 ; + END + END rw0_wmask_in[166] + PIN rw0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 38.406 16.975 38.448 ; + END + END rw0_wmask_in[167] + PIN rw0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.185 38.406 17.199 38.448 ; + END + END rw0_wmask_in[168] + PIN rw0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.409 38.406 17.423 38.448 ; + END + END rw0_wmask_in[169] + PIN rw0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.633 38.406 17.647 38.448 ; + END + END rw0_wmask_in[170] + PIN rw0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.857 38.406 17.871 38.448 ; + END + END rw0_wmask_in[171] + PIN rw0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.081 38.406 18.095 38.448 ; + END + END rw0_wmask_in[172] + PIN rw0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.305 38.406 18.319 38.448 ; + END + END rw0_wmask_in[173] + PIN rw0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.529 38.406 18.543 38.448 ; + END + END rw0_wmask_in[174] + PIN rw0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.753 38.406 18.767 38.448 ; + END + END rw0_wmask_in[175] + PIN rw0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.977 38.406 18.991 38.448 ; + END + END rw0_wmask_in[176] + PIN rw0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.201 38.406 19.215 38.448 ; + END + END rw0_wmask_in[177] + PIN rw0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.425 38.406 19.439 38.448 ; + END + END rw0_wmask_in[178] + PIN rw0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.649 38.406 19.663 38.448 ; + END + END rw0_wmask_in[179] + PIN rw0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.873 38.406 19.887 38.448 ; + END + END rw0_wmask_in[180] + PIN rw0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.097 38.406 20.111 38.448 ; + END + END rw0_wmask_in[181] + PIN rw0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.321 38.406 20.335 38.448 ; + END + END rw0_wmask_in[182] + PIN rw0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.545 38.406 20.559 38.448 ; + END + END rw0_wmask_in[183] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.802 0.036 17.814 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.186 0.036 18.198 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.570 0.036 18.582 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.954 0.036 18.966 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.338 0.036 19.350 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 19.722 0.036 19.734 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.106 0.036 20.118 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.490 0.036 20.502 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 20.874 0.036 20.886 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 21.258 0.036 21.270 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 21.642 0.036 21.654 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.026 0.036 22.038 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.410 0.036 22.422 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 22.794 0.036 22.806 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.178 0.036 23.190 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.562 0.036 23.574 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 23.946 0.036 23.958 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 24.330 0.036 24.342 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 24.714 0.036 24.726 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.098 0.036 25.110 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.482 0.036 25.494 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 25.866 0.036 25.878 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 26.250 0.036 26.262 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 26.634 0.036 26.646 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 27.018 0.036 27.030 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 27.402 0.036 27.414 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 27.786 0.036 27.798 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.170 0.036 28.182 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.554 0.036 28.566 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 28.938 0.036 28.950 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 29.322 0.036 29.334 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 29.706 0.036 29.718 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 30.090 0.036 30.102 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 30.474 0.036 30.486 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 30.858 0.036 30.870 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 31.242 0.036 31.254 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 31.626 0.036 31.638 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 32.010 0.036 32.022 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 32.394 0.036 32.406 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 32.778 0.036 32.790 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 33.162 0.036 33.174 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 33.546 0.036 33.558 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 33.930 0.036 33.942 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 34.314 0.036 34.326 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 34.698 0.036 34.710 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 35.082 0.036 35.094 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 17.802 44.100 17.814 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 18.186 44.100 18.198 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 18.570 44.100 18.582 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 18.954 44.100 18.966 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 19.338 44.100 19.350 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 19.722 44.100 19.734 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 20.106 44.100 20.118 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 20.490 44.100 20.502 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 20.874 44.100 20.886 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 21.258 44.100 21.270 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 21.642 44.100 21.654 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 22.026 44.100 22.038 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 22.410 44.100 22.422 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 22.794 44.100 22.806 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 23.178 44.100 23.190 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 23.562 44.100 23.574 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 23.946 44.100 23.958 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 24.330 44.100 24.342 ; + END + END rw0_wd_in[63] + PIN rw0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 24.714 44.100 24.726 ; + END + END rw0_wd_in[64] + PIN rw0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 25.098 44.100 25.110 ; + END + END rw0_wd_in[65] + PIN rw0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 25.482 44.100 25.494 ; + END + END rw0_wd_in[66] + PIN rw0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 25.866 44.100 25.878 ; + END + END rw0_wd_in[67] + PIN rw0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 26.250 44.100 26.262 ; + END + END rw0_wd_in[68] + PIN rw0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 26.634 44.100 26.646 ; + END + END rw0_wd_in[69] + PIN rw0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 27.018 44.100 27.030 ; + END + END rw0_wd_in[70] + PIN rw0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 27.402 44.100 27.414 ; + END + END rw0_wd_in[71] + PIN rw0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 27.786 44.100 27.798 ; + END + END rw0_wd_in[72] + PIN rw0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 28.170 44.100 28.182 ; + END + END rw0_wd_in[73] + PIN rw0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 28.554 44.100 28.566 ; + END + END rw0_wd_in[74] + PIN rw0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 28.938 44.100 28.950 ; + END + END rw0_wd_in[75] + PIN rw0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 29.322 44.100 29.334 ; + END + END rw0_wd_in[76] + PIN rw0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 29.706 44.100 29.718 ; + END + END rw0_wd_in[77] + PIN rw0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 30.090 44.100 30.102 ; + END + END rw0_wd_in[78] + PIN rw0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 30.474 44.100 30.486 ; + END + END rw0_wd_in[79] + PIN rw0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 30.858 44.100 30.870 ; + END + END rw0_wd_in[80] + PIN rw0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 31.242 44.100 31.254 ; + END + END rw0_wd_in[81] + PIN rw0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 31.626 44.100 31.638 ; + END + END rw0_wd_in[82] + PIN rw0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 32.010 44.100 32.022 ; + END + END rw0_wd_in[83] + PIN rw0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 32.394 44.100 32.406 ; + END + END rw0_wd_in[84] + PIN rw0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 32.778 44.100 32.790 ; + END + END rw0_wd_in[85] + PIN rw0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 33.162 44.100 33.174 ; + END + END rw0_wd_in[86] + PIN rw0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 33.546 44.100 33.558 ; + END + END rw0_wd_in[87] + PIN rw0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 33.930 44.100 33.942 ; + END + END rw0_wd_in[88] + PIN rw0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 34.314 44.100 34.326 ; + END + END rw0_wd_in[89] + PIN rw0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 34.698 44.100 34.710 ; + END + END rw0_wd_in[90] + PIN rw0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 35.082 44.100 35.094 ; + END + END rw0_wd_in[91] + PIN rw0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END rw0_wd_in[92] + PIN rw0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.385 0.000 0.399 0.042 ; + END + END rw0_wd_in[93] + PIN rw0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.609 0.000 0.623 0.042 ; + END + END rw0_wd_in[94] + PIN rw0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.833 0.000 0.847 0.042 ; + END + END rw0_wd_in[95] + PIN rw0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.057 0.000 1.071 0.042 ; + END + END rw0_wd_in[96] + PIN rw0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.281 0.000 1.295 0.042 ; + END + END rw0_wd_in[97] + PIN rw0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.505 0.000 1.519 0.042 ; + END + END rw0_wd_in[98] + PIN rw0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.729 0.000 1.743 0.042 ; + END + END rw0_wd_in[99] + PIN rw0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.953 0.000 1.967 0.042 ; + END + END rw0_wd_in[100] + PIN rw0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.177 0.000 2.191 0.042 ; + END + END rw0_wd_in[101] + PIN rw0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.401 0.000 2.415 0.042 ; + END + END rw0_wd_in[102] + PIN rw0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.625 0.000 2.639 0.042 ; + END + END rw0_wd_in[103] + PIN rw0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 0.000 2.863 0.042 ; + END + END rw0_wd_in[104] + PIN rw0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.073 0.000 3.087 0.042 ; + END + END rw0_wd_in[105] + PIN rw0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.297 0.000 3.311 0.042 ; + END + END rw0_wd_in[106] + PIN rw0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.521 0.000 3.535 0.042 ; + END + END rw0_wd_in[107] + PIN rw0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.745 0.000 3.759 0.042 ; + END + END rw0_wd_in[108] + PIN rw0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.969 0.000 3.983 0.042 ; + END + END rw0_wd_in[109] + PIN rw0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.193 0.000 4.207 0.042 ; + END + END rw0_wd_in[110] + PIN rw0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.417 0.000 4.431 0.042 ; + END + END rw0_wd_in[111] + PIN rw0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.641 0.000 4.655 0.042 ; + END + END rw0_wd_in[112] + PIN rw0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.865 0.000 4.879 0.042 ; + END + END rw0_wd_in[113] + PIN rw0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.089 0.000 5.103 0.042 ; + END + END rw0_wd_in[114] + PIN rw0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.313 0.000 5.327 0.042 ; + END + END rw0_wd_in[115] + PIN rw0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 0.000 5.551 0.042 ; + END + END rw0_wd_in[116] + PIN rw0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.761 0.000 5.775 0.042 ; + END + END rw0_wd_in[117] + PIN rw0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.985 0.000 5.999 0.042 ; + END + END rw0_wd_in[118] + PIN rw0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.209 0.000 6.223 0.042 ; + END + END rw0_wd_in[119] + PIN rw0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.433 0.000 6.447 0.042 ; + END + END rw0_wd_in[120] + PIN rw0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.657 0.000 6.671 0.042 ; + END + END rw0_wd_in[121] + PIN rw0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 0.000 6.895 0.042 ; + END + END rw0_wd_in[122] + PIN rw0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.105 0.000 7.119 0.042 ; + END + END rw0_wd_in[123] + PIN rw0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.329 0.000 7.343 0.042 ; + END + END rw0_wd_in[124] + PIN rw0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.553 0.000 7.567 0.042 ; + END + END rw0_wd_in[125] + PIN rw0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.777 0.000 7.791 0.042 ; + END + END rw0_wd_in[126] + PIN rw0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.001 0.000 8.015 0.042 ; + END + END rw0_wd_in[127] + PIN rw0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 0.000 8.239 0.042 ; + END + END rw0_wd_in[128] + PIN rw0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.449 0.000 8.463 0.042 ; + END + END rw0_wd_in[129] + PIN rw0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.673 0.000 8.687 0.042 ; + END + END rw0_wd_in[130] + PIN rw0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.897 0.000 8.911 0.042 ; + END + END rw0_wd_in[131] + PIN rw0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.121 0.000 9.135 0.042 ; + END + END rw0_wd_in[132] + PIN rw0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.345 0.000 9.359 0.042 ; + END + END rw0_wd_in[133] + PIN rw0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 0.000 9.583 0.042 ; + END + END rw0_wd_in[134] + PIN rw0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.793 0.000 9.807 0.042 ; + END + END rw0_wd_in[135] + PIN rw0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.017 0.000 10.031 0.042 ; + END + END rw0_wd_in[136] + PIN rw0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.241 0.000 10.255 0.042 ; + END + END rw0_wd_in[137] + PIN rw0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.465 0.000 10.479 0.042 ; + END + END rw0_wd_in[138] + PIN rw0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.689 0.000 10.703 0.042 ; + END + END rw0_wd_in[139] + PIN rw0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 0.000 10.927 0.042 ; + END + END rw0_wd_in[140] + PIN rw0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.137 0.000 11.151 0.042 ; + END + END rw0_wd_in[141] + PIN rw0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END rw0_wd_in[142] + PIN rw0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.585 0.000 11.599 0.042 ; + END + END rw0_wd_in[143] + PIN rw0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.809 0.000 11.823 0.042 ; + END + END rw0_wd_in[144] + PIN rw0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.033 0.000 12.047 0.042 ; + END + END rw0_wd_in[145] + PIN rw0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.257 0.000 12.271 0.042 ; + END + END rw0_wd_in[146] + PIN rw0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.481 0.000 12.495 0.042 ; + END + END rw0_wd_in[147] + PIN rw0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.705 0.000 12.719 0.042 ; + END + END rw0_wd_in[148] + PIN rw0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.929 0.000 12.943 0.042 ; + END + END rw0_wd_in[149] + PIN rw0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.153 0.000 13.167 0.042 ; + END + END rw0_wd_in[150] + PIN rw0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.377 0.000 13.391 0.042 ; + END + END rw0_wd_in[151] + PIN rw0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 0.000 13.615 0.042 ; + END + END rw0_wd_in[152] + PIN rw0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.825 0.000 13.839 0.042 ; + END + END rw0_wd_in[153] + PIN rw0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.049 0.000 14.063 0.042 ; + END + END rw0_wd_in[154] + PIN rw0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.273 0.000 14.287 0.042 ; + END + END rw0_wd_in[155] + PIN rw0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.497 0.000 14.511 0.042 ; + END + END rw0_wd_in[156] + PIN rw0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.721 0.000 14.735 0.042 ; + END + END rw0_wd_in[157] + PIN rw0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.945 0.000 14.959 0.042 ; + END + END rw0_wd_in[158] + PIN rw0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.169 0.000 15.183 0.042 ; + END + END rw0_wd_in[159] + PIN rw0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.393 0.000 15.407 0.042 ; + END + END rw0_wd_in[160] + PIN rw0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.617 0.000 15.631 0.042 ; + END + END rw0_wd_in[161] + PIN rw0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.841 0.000 15.855 0.042 ; + END + END rw0_wd_in[162] + PIN rw0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.065 0.000 16.079 0.042 ; + END + END rw0_wd_in[163] + PIN rw0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.289 0.000 16.303 0.042 ; + END + END rw0_wd_in[164] + PIN rw0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.513 0.000 16.527 0.042 ; + END + END rw0_wd_in[165] + PIN rw0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.737 0.000 16.751 0.042 ; + END + END rw0_wd_in[166] + PIN rw0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 0.000 16.975 0.042 ; + END + END rw0_wd_in[167] + PIN rw0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.185 0.000 17.199 0.042 ; + END + END rw0_wd_in[168] + PIN rw0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.409 0.000 17.423 0.042 ; + END + END rw0_wd_in[169] + PIN rw0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.633 0.000 17.647 0.042 ; + END + END rw0_wd_in[170] + PIN rw0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.857 0.000 17.871 0.042 ; + END + END rw0_wd_in[171] + PIN rw0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.081 0.000 18.095 0.042 ; + END + END rw0_wd_in[172] + PIN rw0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.305 0.000 18.319 0.042 ; + END + END rw0_wd_in[173] + PIN rw0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.529 0.000 18.543 0.042 ; + END + END rw0_wd_in[174] + PIN rw0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.753 0.000 18.767 0.042 ; + END + END rw0_wd_in[175] + PIN rw0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.977 0.000 18.991 0.042 ; + END + END rw0_wd_in[176] + PIN rw0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.201 0.000 19.215 0.042 ; + END + END rw0_wd_in[177] + PIN rw0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.425 0.000 19.439 0.042 ; + END + END rw0_wd_in[178] + PIN rw0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.649 0.000 19.663 0.042 ; + END + END rw0_wd_in[179] + PIN rw0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.873 0.000 19.887 0.042 ; + END + END rw0_wd_in[180] + PIN rw0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.097 0.000 20.111 0.042 ; + END + END rw0_wd_in[181] + PIN rw0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.321 0.000 20.335 0.042 ; + END + END rw0_wd_in[182] + PIN rw0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.545 0.000 20.559 0.042 ; + END + END rw0_wd_in[183] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.769 0.000 20.783 0.042 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.993 0.000 21.007 0.042 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.217 0.000 21.231 0.042 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.441 0.000 21.455 0.042 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.665 0.000 21.679 0.042 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.889 0.000 21.903 0.042 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.113 0.000 22.127 0.042 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.337 0.000 22.351 0.042 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 0.000 22.575 0.042 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.785 0.000 22.799 0.042 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.009 0.000 23.023 0.042 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.233 0.000 23.247 0.042 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.457 0.000 23.471 0.042 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.681 0.000 23.695 0.042 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.905 0.000 23.919 0.042 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.129 0.000 24.143 0.042 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.353 0.000 24.367 0.042 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.577 0.000 24.591 0.042 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.801 0.000 24.815 0.042 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.025 0.000 25.039 0.042 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.249 0.000 25.263 0.042 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.473 0.000 25.487 0.042 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.697 0.000 25.711 0.042 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.921 0.000 25.935 0.042 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.145 0.000 26.159 0.042 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.369 0.000 26.383 0.042 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.593 0.000 26.607 0.042 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.817 0.000 26.831 0.042 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.041 0.000 27.055 0.042 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.265 0.000 27.279 0.042 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.489 0.000 27.503 0.042 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.713 0.000 27.727 0.042 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.937 0.000 27.951 0.042 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.161 0.000 28.175 0.042 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.385 0.000 28.399 0.042 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.609 0.000 28.623 0.042 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.833 0.000 28.847 0.042 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.057 0.000 29.071 0.042 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.281 0.000 29.295 0.042 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.505 0.000 29.519 0.042 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.729 0.000 29.743 0.042 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.953 0.000 29.967 0.042 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.177 0.000 30.191 0.042 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.401 0.000 30.415 0.042 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.625 0.000 30.639 0.042 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.849 0.000 30.863 0.042 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.073 0.000 31.087 0.042 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.297 0.000 31.311 0.042 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.521 0.000 31.535 0.042 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.745 0.000 31.759 0.042 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.969 0.000 31.983 0.042 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.193 0.000 32.207 0.042 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.417 0.000 32.431 0.042 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.641 0.000 32.655 0.042 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.865 0.000 32.879 0.042 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.089 0.000 33.103 0.042 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.313 0.000 33.327 0.042 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.537 0.000 33.551 0.042 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.761 0.000 33.775 0.042 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.985 0.000 33.999 0.042 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.209 0.000 34.223 0.042 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.433 0.000 34.447 0.042 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.657 0.000 34.671 0.042 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.881 0.000 34.895 0.042 ; + END + END rw0_rd_out[63] + PIN rw0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.105 0.000 35.119 0.042 ; + END + END rw0_rd_out[64] + PIN rw0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.329 0.000 35.343 0.042 ; + END + END rw0_rd_out[65] + PIN rw0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.553 0.000 35.567 0.042 ; + END + END rw0_rd_out[66] + PIN rw0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.777 0.000 35.791 0.042 ; + END + END rw0_rd_out[67] + PIN rw0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.001 0.000 36.015 0.042 ; + END + END rw0_rd_out[68] + PIN rw0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.225 0.000 36.239 0.042 ; + END + END rw0_rd_out[69] + PIN rw0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.449 0.000 36.463 0.042 ; + END + END rw0_rd_out[70] + PIN rw0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.673 0.000 36.687 0.042 ; + END + END rw0_rd_out[71] + PIN rw0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.897 0.000 36.911 0.042 ; + END + END rw0_rd_out[72] + PIN rw0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.121 0.000 37.135 0.042 ; + END + END rw0_rd_out[73] + PIN rw0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.345 0.000 37.359 0.042 ; + END + END rw0_rd_out[74] + PIN rw0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.569 0.000 37.583 0.042 ; + END + END rw0_rd_out[75] + PIN rw0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.793 0.000 37.807 0.042 ; + END + END rw0_rd_out[76] + PIN rw0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.017 0.000 38.031 0.042 ; + END + END rw0_rd_out[77] + PIN rw0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.241 0.000 38.255 0.042 ; + END + END rw0_rd_out[78] + PIN rw0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.465 0.000 38.479 0.042 ; + END + END rw0_rd_out[79] + PIN rw0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.689 0.000 38.703 0.042 ; + END + END rw0_rd_out[80] + PIN rw0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.913 0.000 38.927 0.042 ; + END + END rw0_rd_out[81] + PIN rw0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.137 0.000 39.151 0.042 ; + END + END rw0_rd_out[82] + PIN rw0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.361 0.000 39.375 0.042 ; + END + END rw0_rd_out[83] + PIN rw0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.585 0.000 39.599 0.042 ; + END + END rw0_rd_out[84] + PIN rw0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.809 0.000 39.823 0.042 ; + END + END rw0_rd_out[85] + PIN rw0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.033 0.000 40.047 0.042 ; + END + END rw0_rd_out[86] + PIN rw0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.257 0.000 40.271 0.042 ; + END + END rw0_rd_out[87] + PIN rw0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.481 0.000 40.495 0.042 ; + END + END rw0_rd_out[88] + PIN rw0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.705 0.000 40.719 0.042 ; + END + END rw0_rd_out[89] + PIN rw0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.929 0.000 40.943 0.042 ; + END + END rw0_rd_out[90] + PIN rw0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.153 0.000 41.167 0.042 ; + END + END rw0_rd_out[91] + PIN rw0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.769 38.406 20.783 38.448 ; + END + END rw0_rd_out[92] + PIN rw0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.993 38.406 21.007 38.448 ; + END + END rw0_rd_out[93] + PIN rw0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.217 38.406 21.231 38.448 ; + END + END rw0_rd_out[94] + PIN rw0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.441 38.406 21.455 38.448 ; + END + END rw0_rd_out[95] + PIN rw0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.665 38.406 21.679 38.448 ; + END + END rw0_rd_out[96] + PIN rw0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.889 38.406 21.903 38.448 ; + END + END rw0_rd_out[97] + PIN rw0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.113 38.406 22.127 38.448 ; + END + END rw0_rd_out[98] + PIN rw0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.337 38.406 22.351 38.448 ; + END + END rw0_rd_out[99] + PIN rw0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.561 38.406 22.575 38.448 ; + END + END rw0_rd_out[100] + PIN rw0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.785 38.406 22.799 38.448 ; + END + END rw0_rd_out[101] + PIN rw0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.009 38.406 23.023 38.448 ; + END + END rw0_rd_out[102] + PIN rw0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.233 38.406 23.247 38.448 ; + END + END rw0_rd_out[103] + PIN rw0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.457 38.406 23.471 38.448 ; + END + END rw0_rd_out[104] + PIN rw0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.681 38.406 23.695 38.448 ; + END + END rw0_rd_out[105] + PIN rw0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.905 38.406 23.919 38.448 ; + END + END rw0_rd_out[106] + PIN rw0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.129 38.406 24.143 38.448 ; + END + END rw0_rd_out[107] + PIN rw0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.353 38.406 24.367 38.448 ; + END + END rw0_rd_out[108] + PIN rw0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.577 38.406 24.591 38.448 ; + END + END rw0_rd_out[109] + PIN rw0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.801 38.406 24.815 38.448 ; + END + END rw0_rd_out[110] + PIN rw0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.025 38.406 25.039 38.448 ; + END + END rw0_rd_out[111] + PIN rw0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.249 38.406 25.263 38.448 ; + END + END rw0_rd_out[112] + PIN rw0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.473 38.406 25.487 38.448 ; + END + END rw0_rd_out[113] + PIN rw0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.697 38.406 25.711 38.448 ; + END + END rw0_rd_out[114] + PIN rw0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.921 38.406 25.935 38.448 ; + END + END rw0_rd_out[115] + PIN rw0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.145 38.406 26.159 38.448 ; + END + END rw0_rd_out[116] + PIN rw0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.369 38.406 26.383 38.448 ; + END + END rw0_rd_out[117] + PIN rw0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.593 38.406 26.607 38.448 ; + END + END rw0_rd_out[118] + PIN rw0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.817 38.406 26.831 38.448 ; + END + END rw0_rd_out[119] + PIN rw0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.041 38.406 27.055 38.448 ; + END + END rw0_rd_out[120] + PIN rw0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.265 38.406 27.279 38.448 ; + END + END rw0_rd_out[121] + PIN rw0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.489 38.406 27.503 38.448 ; + END + END rw0_rd_out[122] + PIN rw0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.713 38.406 27.727 38.448 ; + END + END rw0_rd_out[123] + PIN rw0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.937 38.406 27.951 38.448 ; + END + END rw0_rd_out[124] + PIN rw0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.161 38.406 28.175 38.448 ; + END + END rw0_rd_out[125] + PIN rw0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.385 38.406 28.399 38.448 ; + END + END rw0_rd_out[126] + PIN rw0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.609 38.406 28.623 38.448 ; + END + END rw0_rd_out[127] + PIN rw0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.833 38.406 28.847 38.448 ; + END + END rw0_rd_out[128] + PIN rw0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.057 38.406 29.071 38.448 ; + END + END rw0_rd_out[129] + PIN rw0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.281 38.406 29.295 38.448 ; + END + END rw0_rd_out[130] + PIN rw0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.505 38.406 29.519 38.448 ; + END + END rw0_rd_out[131] + PIN rw0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.729 38.406 29.743 38.448 ; + END + END rw0_rd_out[132] + PIN rw0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.953 38.406 29.967 38.448 ; + END + END rw0_rd_out[133] + PIN rw0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.177 38.406 30.191 38.448 ; + END + END rw0_rd_out[134] + PIN rw0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.401 38.406 30.415 38.448 ; + END + END rw0_rd_out[135] + PIN rw0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.625 38.406 30.639 38.448 ; + END + END rw0_rd_out[136] + PIN rw0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.849 38.406 30.863 38.448 ; + END + END rw0_rd_out[137] + PIN rw0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.073 38.406 31.087 38.448 ; + END + END rw0_rd_out[138] + PIN rw0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.297 38.406 31.311 38.448 ; + END + END rw0_rd_out[139] + PIN rw0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.521 38.406 31.535 38.448 ; + END + END rw0_rd_out[140] + PIN rw0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.745 38.406 31.759 38.448 ; + END + END rw0_rd_out[141] + PIN rw0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.969 38.406 31.983 38.448 ; + END + END rw0_rd_out[142] + PIN rw0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.193 38.406 32.207 38.448 ; + END + END rw0_rd_out[143] + PIN rw0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.417 38.406 32.431 38.448 ; + END + END rw0_rd_out[144] + PIN rw0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.641 38.406 32.655 38.448 ; + END + END rw0_rd_out[145] + PIN rw0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.865 38.406 32.879 38.448 ; + END + END rw0_rd_out[146] + PIN rw0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.089 38.406 33.103 38.448 ; + END + END rw0_rd_out[147] + PIN rw0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.313 38.406 33.327 38.448 ; + END + END rw0_rd_out[148] + PIN rw0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.537 38.406 33.551 38.448 ; + END + END rw0_rd_out[149] + PIN rw0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.761 38.406 33.775 38.448 ; + END + END rw0_rd_out[150] + PIN rw0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.985 38.406 33.999 38.448 ; + END + END rw0_rd_out[151] + PIN rw0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.209 38.406 34.223 38.448 ; + END + END rw0_rd_out[152] + PIN rw0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.433 38.406 34.447 38.448 ; + END + END rw0_rd_out[153] + PIN rw0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.657 38.406 34.671 38.448 ; + END + END rw0_rd_out[154] + PIN rw0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.881 38.406 34.895 38.448 ; + END + END rw0_rd_out[155] + PIN rw0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.105 38.406 35.119 38.448 ; + END + END rw0_rd_out[156] + PIN rw0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.329 38.406 35.343 38.448 ; + END + END rw0_rd_out[157] + PIN rw0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.553 38.406 35.567 38.448 ; + END + END rw0_rd_out[158] + PIN rw0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.777 38.406 35.791 38.448 ; + END + END rw0_rd_out[159] + PIN rw0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.001 38.406 36.015 38.448 ; + END + END rw0_rd_out[160] + PIN rw0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.225 38.406 36.239 38.448 ; + END + END rw0_rd_out[161] + PIN rw0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.449 38.406 36.463 38.448 ; + END + END rw0_rd_out[162] + PIN rw0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.673 38.406 36.687 38.448 ; + END + END rw0_rd_out[163] + PIN rw0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.897 38.406 36.911 38.448 ; + END + END rw0_rd_out[164] + PIN rw0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.121 38.406 37.135 38.448 ; + END + END rw0_rd_out[165] + PIN rw0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.345 38.406 37.359 38.448 ; + END + END rw0_rd_out[166] + PIN rw0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.569 38.406 37.583 38.448 ; + END + END rw0_rd_out[167] + PIN rw0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.793 38.406 37.807 38.448 ; + END + END rw0_rd_out[168] + PIN rw0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.017 38.406 38.031 38.448 ; + END + END rw0_rd_out[169] + PIN rw0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.241 38.406 38.255 38.448 ; + END + END rw0_rd_out[170] + PIN rw0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.465 38.406 38.479 38.448 ; + END + END rw0_rd_out[171] + PIN rw0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.689 38.406 38.703 38.448 ; + END + END rw0_rd_out[172] + PIN rw0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.913 38.406 38.927 38.448 ; + END + END rw0_rd_out[173] + PIN rw0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.137 38.406 39.151 38.448 ; + END + END rw0_rd_out[174] + PIN rw0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.361 38.406 39.375 38.448 ; + END + END rw0_rd_out[175] + PIN rw0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.585 38.406 39.599 38.448 ; + END + END rw0_rd_out[176] + PIN rw0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.809 38.406 39.823 38.448 ; + END + END rw0_rd_out[177] + PIN rw0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.033 38.406 40.047 38.448 ; + END + END rw0_rd_out[178] + PIN rw0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.257 38.406 40.271 38.448 ; + END + END rw0_rd_out[179] + PIN rw0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.481 38.406 40.495 38.448 ; + END + END rw0_rd_out[180] + PIN rw0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.705 38.406 40.719 38.448 ; + END + END rw0_rd_out[181] + PIN rw0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.929 38.406 40.943 38.448 ; + END + END rw0_rd_out[182] + PIN rw0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.153 38.406 41.167 38.448 ; + END + END rw0_rd_out[183] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 35.466 0.036 35.478 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 35.850 0.036 35.862 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 36.234 0.036 36.246 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 35.466 44.100 35.478 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 35.850 44.100 35.862 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 44.064 36.234 44.100 36.246 ; + END + END rw0_addr_in[5] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.377 38.406 41.391 38.448 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.601 38.406 41.615 38.448 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.825 38.406 41.839 38.448 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 43.932 0.168 ; + RECT 0.168 0.504 43.932 0.552 ; + RECT 0.168 0.888 43.932 0.936 ; + RECT 0.168 1.272 43.932 1.320 ; + RECT 0.168 1.656 43.932 1.704 ; + RECT 0.168 2.040 43.932 2.088 ; + RECT 0.168 2.424 43.932 2.472 ; + RECT 0.168 2.808 43.932 2.856 ; + RECT 0.168 3.192 43.932 3.240 ; + RECT 0.168 3.576 43.932 3.624 ; + RECT 0.168 3.960 43.932 4.008 ; + RECT 0.168 4.344 43.932 4.392 ; + RECT 0.168 4.728 43.932 4.776 ; + RECT 0.168 5.112 43.932 5.160 ; + RECT 0.168 5.496 43.932 5.544 ; + RECT 0.168 5.880 43.932 5.928 ; + RECT 0.168 6.264 43.932 6.312 ; + RECT 0.168 6.648 43.932 6.696 ; + RECT 0.168 7.032 43.932 7.080 ; + RECT 0.168 7.416 43.932 7.464 ; + RECT 0.168 7.800 43.932 7.848 ; + RECT 0.168 8.184 43.932 8.232 ; + RECT 0.168 8.568 43.932 8.616 ; + RECT 0.168 8.952 43.932 9.000 ; + RECT 0.168 9.336 43.932 9.384 ; + RECT 0.168 9.720 43.932 9.768 ; + RECT 0.168 10.104 43.932 10.152 ; + RECT 0.168 10.488 43.932 10.536 ; + RECT 0.168 10.872 43.932 10.920 ; + RECT 0.168 11.256 43.932 11.304 ; + RECT 0.168 11.640 43.932 11.688 ; + RECT 0.168 12.024 43.932 12.072 ; + RECT 0.168 12.408 43.932 12.456 ; + RECT 0.168 12.792 43.932 12.840 ; + RECT 0.168 13.176 43.932 13.224 ; + RECT 0.168 13.560 43.932 13.608 ; + RECT 0.168 13.944 43.932 13.992 ; + RECT 0.168 14.328 43.932 14.376 ; + RECT 0.168 14.712 43.932 14.760 ; + RECT 0.168 15.096 43.932 15.144 ; + RECT 0.168 15.480 43.932 15.528 ; + RECT 0.168 15.864 43.932 15.912 ; + RECT 0.168 16.248 43.932 16.296 ; + RECT 0.168 16.632 43.932 16.680 ; + RECT 0.168 17.016 43.932 17.064 ; + RECT 0.168 17.400 43.932 17.448 ; + RECT 0.168 17.784 43.932 17.832 ; + RECT 0.168 18.168 43.932 18.216 ; + RECT 0.168 18.552 43.932 18.600 ; + RECT 0.168 18.936 43.932 18.984 ; + RECT 0.168 19.320 43.932 19.368 ; + RECT 0.168 19.704 43.932 19.752 ; + RECT 0.168 20.088 43.932 20.136 ; + RECT 0.168 20.472 43.932 20.520 ; + RECT 0.168 20.856 43.932 20.904 ; + RECT 0.168 21.240 43.932 21.288 ; + RECT 0.168 21.624 43.932 21.672 ; + RECT 0.168 22.008 43.932 22.056 ; + RECT 0.168 22.392 43.932 22.440 ; + RECT 0.168 22.776 43.932 22.824 ; + RECT 0.168 23.160 43.932 23.208 ; + RECT 0.168 23.544 43.932 23.592 ; + RECT 0.168 23.928 43.932 23.976 ; + RECT 0.168 24.312 43.932 24.360 ; + RECT 0.168 24.696 43.932 24.744 ; + RECT 0.168 25.080 43.932 25.128 ; + RECT 0.168 25.464 43.932 25.512 ; + RECT 0.168 25.848 43.932 25.896 ; + RECT 0.168 26.232 43.932 26.280 ; + RECT 0.168 26.616 43.932 26.664 ; + RECT 0.168 27.000 43.932 27.048 ; + RECT 0.168 27.384 43.932 27.432 ; + RECT 0.168 27.768 43.932 27.816 ; + RECT 0.168 28.152 43.932 28.200 ; + RECT 0.168 28.536 43.932 28.584 ; + RECT 0.168 28.920 43.932 28.968 ; + RECT 0.168 29.304 43.932 29.352 ; + RECT 0.168 29.688 43.932 29.736 ; + RECT 0.168 30.072 43.932 30.120 ; + RECT 0.168 30.456 43.932 30.504 ; + RECT 0.168 30.840 43.932 30.888 ; + RECT 0.168 31.224 43.932 31.272 ; + RECT 0.168 31.608 43.932 31.656 ; + RECT 0.168 31.992 43.932 32.040 ; + RECT 0.168 32.376 43.932 32.424 ; + RECT 0.168 32.760 43.932 32.808 ; + RECT 0.168 33.144 43.932 33.192 ; + RECT 0.168 33.528 43.932 33.576 ; + RECT 0.168 33.912 43.932 33.960 ; + RECT 0.168 34.296 43.932 34.344 ; + RECT 0.168 34.680 43.932 34.728 ; + RECT 0.168 35.064 43.932 35.112 ; + RECT 0.168 35.448 43.932 35.496 ; + RECT 0.168 35.832 43.932 35.880 ; + RECT 0.168 36.216 43.932 36.264 ; + RECT 0.168 36.600 43.932 36.648 ; + RECT 0.168 36.984 43.932 37.032 ; + RECT 0.168 37.368 43.932 37.416 ; + RECT 0.168 37.752 43.932 37.800 ; + RECT 0.168 38.136 43.932 38.184 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.312 43.932 0.360 ; + RECT 0.168 0.696 43.932 0.744 ; + RECT 0.168 1.080 43.932 1.128 ; + RECT 0.168 1.464 43.932 1.512 ; + RECT 0.168 1.848 43.932 1.896 ; + RECT 0.168 2.232 43.932 2.280 ; + RECT 0.168 2.616 43.932 2.664 ; + RECT 0.168 3.000 43.932 3.048 ; + RECT 0.168 3.384 43.932 3.432 ; + RECT 0.168 3.768 43.932 3.816 ; + RECT 0.168 4.152 43.932 4.200 ; + RECT 0.168 4.536 43.932 4.584 ; + RECT 0.168 4.920 43.932 4.968 ; + RECT 0.168 5.304 43.932 5.352 ; + RECT 0.168 5.688 43.932 5.736 ; + RECT 0.168 6.072 43.932 6.120 ; + RECT 0.168 6.456 43.932 6.504 ; + RECT 0.168 6.840 43.932 6.888 ; + RECT 0.168 7.224 43.932 7.272 ; + RECT 0.168 7.608 43.932 7.656 ; + RECT 0.168 7.992 43.932 8.040 ; + RECT 0.168 8.376 43.932 8.424 ; + RECT 0.168 8.760 43.932 8.808 ; + RECT 0.168 9.144 43.932 9.192 ; + RECT 0.168 9.528 43.932 9.576 ; + RECT 0.168 9.912 43.932 9.960 ; + RECT 0.168 10.296 43.932 10.344 ; + RECT 0.168 10.680 43.932 10.728 ; + RECT 0.168 11.064 43.932 11.112 ; + RECT 0.168 11.448 43.932 11.496 ; + RECT 0.168 11.832 43.932 11.880 ; + RECT 0.168 12.216 43.932 12.264 ; + RECT 0.168 12.600 43.932 12.648 ; + RECT 0.168 12.984 43.932 13.032 ; + RECT 0.168 13.368 43.932 13.416 ; + RECT 0.168 13.752 43.932 13.800 ; + RECT 0.168 14.136 43.932 14.184 ; + RECT 0.168 14.520 43.932 14.568 ; + RECT 0.168 14.904 43.932 14.952 ; + RECT 0.168 15.288 43.932 15.336 ; + RECT 0.168 15.672 43.932 15.720 ; + RECT 0.168 16.056 43.932 16.104 ; + RECT 0.168 16.440 43.932 16.488 ; + RECT 0.168 16.824 43.932 16.872 ; + RECT 0.168 17.208 43.932 17.256 ; + RECT 0.168 17.592 43.932 17.640 ; + RECT 0.168 17.976 43.932 18.024 ; + RECT 0.168 18.360 43.932 18.408 ; + RECT 0.168 18.744 43.932 18.792 ; + RECT 0.168 19.128 43.932 19.176 ; + RECT 0.168 19.512 43.932 19.560 ; + RECT 0.168 19.896 43.932 19.944 ; + RECT 0.168 20.280 43.932 20.328 ; + RECT 0.168 20.664 43.932 20.712 ; + RECT 0.168 21.048 43.932 21.096 ; + RECT 0.168 21.432 43.932 21.480 ; + RECT 0.168 21.816 43.932 21.864 ; + RECT 0.168 22.200 43.932 22.248 ; + RECT 0.168 22.584 43.932 22.632 ; + RECT 0.168 22.968 43.932 23.016 ; + RECT 0.168 23.352 43.932 23.400 ; + RECT 0.168 23.736 43.932 23.784 ; + RECT 0.168 24.120 43.932 24.168 ; + RECT 0.168 24.504 43.932 24.552 ; + RECT 0.168 24.888 43.932 24.936 ; + RECT 0.168 25.272 43.932 25.320 ; + RECT 0.168 25.656 43.932 25.704 ; + RECT 0.168 26.040 43.932 26.088 ; + RECT 0.168 26.424 43.932 26.472 ; + RECT 0.168 26.808 43.932 26.856 ; + RECT 0.168 27.192 43.932 27.240 ; + RECT 0.168 27.576 43.932 27.624 ; + RECT 0.168 27.960 43.932 28.008 ; + RECT 0.168 28.344 43.932 28.392 ; + RECT 0.168 28.728 43.932 28.776 ; + RECT 0.168 29.112 43.932 29.160 ; + RECT 0.168 29.496 43.932 29.544 ; + RECT 0.168 29.880 43.932 29.928 ; + RECT 0.168 30.264 43.932 30.312 ; + RECT 0.168 30.648 43.932 30.696 ; + RECT 0.168 31.032 43.932 31.080 ; + RECT 0.168 31.416 43.932 31.464 ; + RECT 0.168 31.800 43.932 31.848 ; + RECT 0.168 32.184 43.932 32.232 ; + RECT 0.168 32.568 43.932 32.616 ; + RECT 0.168 32.952 43.932 33.000 ; + RECT 0.168 33.336 43.932 33.384 ; + RECT 0.168 33.720 43.932 33.768 ; + RECT 0.168 34.104 43.932 34.152 ; + RECT 0.168 34.488 43.932 34.536 ; + RECT 0.168 34.872 43.932 34.920 ; + RECT 0.168 35.256 43.932 35.304 ; + RECT 0.168 35.640 43.932 35.688 ; + RECT 0.168 36.024 43.932 36.072 ; + RECT 0.168 36.408 43.932 36.456 ; + RECT 0.168 36.792 43.932 36.840 ; + RECT 0.168 37.176 43.932 37.224 ; + RECT 0.168 37.560 43.932 37.608 ; + RECT 0.168 37.944 43.932 37.992 ; + RECT 0.168 38.328 43.932 38.376 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 44.100 38.448 ; + LAYER M2 ; + RECT 0 0 44.100 38.448 ; + LAYER M3 ; + RECT 0 0 44.100 38.448 ; + LAYER M4 ; + RECT 0 0 44.100 38.448 ; + END +END fakeram_64x184_1rw + +END LIBRARY diff --git a/designs/gt2n/bp_processor/sram/lef/fakeram_64x50_1rw.lef b/designs/gt2n/bp_processor/sram/lef/fakeram_64x50_1rw.lef new file mode 100644 index 00000000..c00c0f56 --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lef/fakeram_64x50_1rw.lef @@ -0,0 +1,1565 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x50_1rw + FOREIGN fakeram_64x50_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 23.982 BY 19.296 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.138 0.036 0.150 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 0.810 0.036 0.822 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 1.482 0.036 1.494 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.154 0.036 2.166 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 2.826 0.036 2.838 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 3.498 0.036 3.510 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.170 0.036 4.182 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 4.842 0.036 4.854 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 5.514 0.036 5.526 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.186 0.036 6.198 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 6.858 0.036 6.870 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 7.530 0.036 7.542 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.202 0.036 8.214 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 0.138 23.982 0.150 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 0.810 23.982 0.822 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 1.482 23.982 1.494 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 2.154 23.982 2.166 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 2.826 23.982 2.838 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 3.498 23.982 3.510 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 4.170 23.982 4.182 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 4.842 23.982 4.854 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 5.514 23.982 5.526 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 6.186 23.982 6.198 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 6.858 23.982 6.870 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 7.530 23.982 7.542 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 19.254 0.175 19.296 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.581 19.254 0.595 19.296 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.001 19.254 1.015 19.296 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.421 19.254 1.435 19.296 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.841 19.254 1.855 19.296 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.261 19.254 2.275 19.296 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.681 19.254 2.695 19.296 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.101 19.254 3.115 19.296 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.521 19.254 3.535 19.296 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.941 19.254 3.955 19.296 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.361 19.254 4.375 19.296 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.781 19.254 4.795 19.296 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.201 19.254 5.215 19.296 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.621 19.254 5.635 19.296 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.041 19.254 6.055 19.296 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.461 19.254 6.475 19.296 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 19.254 6.895 19.296 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.301 19.254 7.315 19.296 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.721 19.254 7.735 19.296 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.141 19.254 8.155 19.296 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.561 19.254 8.575 19.296 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.981 19.254 8.995 19.296 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.401 19.254 9.415 19.296 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.821 19.254 9.835 19.296 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.241 19.254 10.255 19.296 ; + END + END rw0_wmask_in[49] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 8.874 0.036 8.886 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 9.546 0.036 9.558 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.218 0.036 10.230 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 10.890 0.036 10.902 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 11.562 0.036 11.574 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.234 0.036 12.246 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 12.906 0.036 12.918 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 13.578 0.036 13.590 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.250 0.036 14.262 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 14.922 0.036 14.934 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 15.594 0.036 15.606 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.266 0.036 16.278 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 16.938 0.036 16.950 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 8.202 23.982 8.214 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 8.874 23.982 8.886 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 9.546 23.982 9.558 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 10.218 23.982 10.230 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 10.890 23.982 10.902 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 11.562 23.982 11.574 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 12.234 23.982 12.246 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 12.906 23.982 12.918 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 13.578 23.982 13.590 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 14.250 23.982 14.262 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 14.922 23.982 14.934 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 15.594 23.982 15.606 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.161 0.000 0.175 0.042 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.609 0.000 0.623 0.042 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.057 0.000 1.071 0.042 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.505 0.000 1.519 0.042 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.953 0.000 1.967 0.042 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.401 0.000 2.415 0.042 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.849 0.000 2.863 0.042 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.297 0.000 3.311 0.042 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.745 0.000 3.759 0.042 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.193 0.000 4.207 0.042 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.641 0.000 4.655 0.042 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.089 0.000 5.103 0.042 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.537 0.000 5.551 0.042 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.985 0.000 5.999 0.042 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.433 0.000 6.447 0.042 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.881 0.000 6.895 0.042 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.329 0.000 7.343 0.042 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.777 0.000 7.791 0.042 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.225 0.000 8.239 0.042 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.673 0.000 8.687 0.042 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.121 0.000 9.135 0.042 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.569 0.000 9.583 0.042 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.017 0.000 10.031 0.042 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.465 0.000 10.479 0.042 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.913 0.000 10.927 0.042 ; + END + END rw0_wd_in[49] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.361 0.000 11.375 0.042 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.809 0.000 11.823 0.042 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.257 0.000 12.271 0.042 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.705 0.000 12.719 0.042 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.153 0.000 13.167 0.042 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 0.000 13.615 0.042 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.049 0.000 14.063 0.042 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.497 0.000 14.511 0.042 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.945 0.000 14.959 0.042 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.393 0.000 15.407 0.042 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.841 0.000 15.855 0.042 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.289 0.000 16.303 0.042 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.737 0.000 16.751 0.042 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.185 0.000 17.199 0.042 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.633 0.000 17.647 0.042 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.081 0.000 18.095 0.042 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.529 0.000 18.543 0.042 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.977 0.000 18.991 0.042 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.425 0.000 19.439 0.042 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.873 0.000 19.887 0.042 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.321 0.000 20.335 0.042 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.769 0.000 20.783 0.042 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.217 0.000 21.231 0.042 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.665 0.000 21.679 0.042 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.113 0.000 22.127 0.042 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.661 19.254 10.675 19.296 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.081 19.254 11.095 19.296 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.501 19.254 11.515 19.296 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.921 19.254 11.935 19.296 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.341 19.254 12.355 19.296 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.761 19.254 12.775 19.296 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.181 19.254 13.195 19.296 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.601 19.254 13.615 19.296 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.021 19.254 14.035 19.296 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.441 19.254 14.455 19.296 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.861 19.254 14.875 19.296 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.281 19.254 15.295 19.296 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.701 19.254 15.715 19.296 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.121 19.254 16.135 19.296 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.541 19.254 16.555 19.296 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.961 19.254 16.975 19.296 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.381 19.254 17.395 19.296 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.801 19.254 17.815 19.296 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.221 19.254 18.235 19.296 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.641 19.254 18.655 19.296 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.061 19.254 19.075 19.296 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.481 19.254 19.495 19.296 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.901 19.254 19.915 19.296 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.321 19.254 20.335 19.296 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.741 19.254 20.755 19.296 ; + END + END rw0_rd_out[49] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 17.610 0.036 17.622 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.282 0.036 18.294 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 0.000 18.954 0.036 18.966 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 16.266 23.982 16.278 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 16.938 23.982 16.950 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M2 ; + RECT 23.946 17.610 23.982 17.622 ; + END + END rw0_addr_in[5] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.161 19.254 21.175 19.296 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.581 19.254 21.595 19.296 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.001 19.254 22.015 19.296 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.168 0.120 23.814 0.168 ; + RECT 0.168 0.504 23.814 0.552 ; + RECT 0.168 0.888 23.814 0.936 ; + RECT 0.168 1.272 23.814 1.320 ; + RECT 0.168 1.656 23.814 1.704 ; + RECT 0.168 2.040 23.814 2.088 ; + RECT 0.168 2.424 23.814 2.472 ; + RECT 0.168 2.808 23.814 2.856 ; + RECT 0.168 3.192 23.814 3.240 ; + RECT 0.168 3.576 23.814 3.624 ; + RECT 0.168 3.960 23.814 4.008 ; + RECT 0.168 4.344 23.814 4.392 ; + RECT 0.168 4.728 23.814 4.776 ; + RECT 0.168 5.112 23.814 5.160 ; + RECT 0.168 5.496 23.814 5.544 ; + RECT 0.168 5.880 23.814 5.928 ; + RECT 0.168 6.264 23.814 6.312 ; + RECT 0.168 6.648 23.814 6.696 ; + RECT 0.168 7.032 23.814 7.080 ; + RECT 0.168 7.416 23.814 7.464 ; + RECT 0.168 7.800 23.814 7.848 ; + RECT 0.168 8.184 23.814 8.232 ; + RECT 0.168 8.568 23.814 8.616 ; + RECT 0.168 8.952 23.814 9.000 ; + RECT 0.168 9.336 23.814 9.384 ; + RECT 0.168 9.720 23.814 9.768 ; + RECT 0.168 10.104 23.814 10.152 ; + RECT 0.168 10.488 23.814 10.536 ; + RECT 0.168 10.872 23.814 10.920 ; + RECT 0.168 11.256 23.814 11.304 ; + RECT 0.168 11.640 23.814 11.688 ; + RECT 0.168 12.024 23.814 12.072 ; + RECT 0.168 12.408 23.814 12.456 ; + RECT 0.168 12.792 23.814 12.840 ; + RECT 0.168 13.176 23.814 13.224 ; + RECT 0.168 13.560 23.814 13.608 ; + RECT 0.168 13.944 23.814 13.992 ; + RECT 0.168 14.328 23.814 14.376 ; + RECT 0.168 14.712 23.814 14.760 ; + RECT 0.168 15.096 23.814 15.144 ; + RECT 0.168 15.480 23.814 15.528 ; + RECT 0.168 15.864 23.814 15.912 ; + RECT 0.168 16.248 23.814 16.296 ; + RECT 0.168 16.632 23.814 16.680 ; + RECT 0.168 17.016 23.814 17.064 ; + RECT 0.168 17.400 23.814 17.448 ; + RECT 0.168 17.784 23.814 17.832 ; + RECT 0.168 18.168 23.814 18.216 ; + RECT 0.168 18.552 23.814 18.600 ; + RECT 0.168 18.936 23.814 18.984 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.168 0.312 23.814 0.360 ; + RECT 0.168 0.696 23.814 0.744 ; + RECT 0.168 1.080 23.814 1.128 ; + RECT 0.168 1.464 23.814 1.512 ; + RECT 0.168 1.848 23.814 1.896 ; + RECT 0.168 2.232 23.814 2.280 ; + RECT 0.168 2.616 23.814 2.664 ; + RECT 0.168 3.000 23.814 3.048 ; + RECT 0.168 3.384 23.814 3.432 ; + RECT 0.168 3.768 23.814 3.816 ; + RECT 0.168 4.152 23.814 4.200 ; + RECT 0.168 4.536 23.814 4.584 ; + RECT 0.168 4.920 23.814 4.968 ; + RECT 0.168 5.304 23.814 5.352 ; + RECT 0.168 5.688 23.814 5.736 ; + RECT 0.168 6.072 23.814 6.120 ; + RECT 0.168 6.456 23.814 6.504 ; + RECT 0.168 6.840 23.814 6.888 ; + RECT 0.168 7.224 23.814 7.272 ; + RECT 0.168 7.608 23.814 7.656 ; + RECT 0.168 7.992 23.814 8.040 ; + RECT 0.168 8.376 23.814 8.424 ; + RECT 0.168 8.760 23.814 8.808 ; + RECT 0.168 9.144 23.814 9.192 ; + RECT 0.168 9.528 23.814 9.576 ; + RECT 0.168 9.912 23.814 9.960 ; + RECT 0.168 10.296 23.814 10.344 ; + RECT 0.168 10.680 23.814 10.728 ; + RECT 0.168 11.064 23.814 11.112 ; + RECT 0.168 11.448 23.814 11.496 ; + RECT 0.168 11.832 23.814 11.880 ; + RECT 0.168 12.216 23.814 12.264 ; + RECT 0.168 12.600 23.814 12.648 ; + RECT 0.168 12.984 23.814 13.032 ; + RECT 0.168 13.368 23.814 13.416 ; + RECT 0.168 13.752 23.814 13.800 ; + RECT 0.168 14.136 23.814 14.184 ; + RECT 0.168 14.520 23.814 14.568 ; + RECT 0.168 14.904 23.814 14.952 ; + RECT 0.168 15.288 23.814 15.336 ; + RECT 0.168 15.672 23.814 15.720 ; + RECT 0.168 16.056 23.814 16.104 ; + RECT 0.168 16.440 23.814 16.488 ; + RECT 0.168 16.824 23.814 16.872 ; + RECT 0.168 17.208 23.814 17.256 ; + RECT 0.168 17.592 23.814 17.640 ; + RECT 0.168 17.976 23.814 18.024 ; + RECT 0.168 18.360 23.814 18.408 ; + RECT 0.168 18.744 23.814 18.792 ; + RECT 0.168 19.128 23.814 19.176 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 23.982 19.296 ; + LAYER M2 ; + RECT 0 0 23.982 19.296 ; + LAYER M3 ; + RECT 0 0 23.982 19.296 ; + LAYER M4 ; + RECT 0 0 23.982 19.296 ; + END +END fakeram_64x50_1rw + +END LIBRARY diff --git a/designs/gt2n/bp_processor/sram/lib/fakeram_128x8_1rw.lib b/designs/gt2n/bp_processor/sram/lib/fakeram_128x8_1rw.lib new file mode 100644 index 00000000..cb9df140 --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lib/fakeram_128x8_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_128x8_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-09-18 18:35:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_128x8_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_128x8_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_128x8_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_128x8_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_128x8_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_128x8_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_128x8_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } + type (fakeram_128x8_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_128x8_1rw) { + area : 148.309; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 8; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.00244; + clock : true; + min_period : 0.143 ; + internal_power(){ + rise_power(fakeram_128x8_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_128x8_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_128x8_1rw_DATA; + direction : output; + max_capacitance : 0.0488; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_128x8_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_128x8_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_128x8_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + fall_transition(fakeram_128x8_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_128x8_1rw_ADDRESS; + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_128x8_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_128x8_1rw_WMASK; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_128x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_128x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/bp_processor/sram/lib/fakeram_32x48_1rw.lib b/designs/gt2n/bp_processor/sram/lib/fakeram_32x48_1rw.lib new file mode 100644 index 00000000..a1fd6095 --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lib/fakeram_32x48_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_32x48_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-09-18 18:35:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_32x48_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_32x48_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_32x48_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_32x48_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_32x48_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_32x48_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 48; + bit_from : 47; + bit_to : 0 ; + downto : true ; + } + type (fakeram_32x48_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } + type (fakeram_32x48_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 48; + bit_from : 47; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_32x48_1rw) { + area : 222.058; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 48; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.00244; + clock : true; + min_period : 0.143 ; + internal_power(){ + rise_power(fakeram_32x48_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_32x48_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_32x48_1rw_DATA; + direction : output; + max_capacitance : 0.0488; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_32x48_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_32x48_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_32x48_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + fall_transition(fakeram_32x48_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_32x48_1rw_ADDRESS; + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_32x48_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_32x48_1rw_WMASK; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_32x48_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_32x48_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/bp_processor/sram/lib/fakeram_512x64_1rw.lib b/designs/gt2n/bp_processor/sram/lib/fakeram_512x64_1rw.lib new file mode 100644 index 00000000..24e9fc39 --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lib/fakeram_512x64_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_512x64_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-09-18 18:35:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_512x64_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_512x64_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_512x64_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_512x64_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_512x64_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_512x64_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x64_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x64_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_512x64_1rw) { + area : 4709.656; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 64; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.00244; + clock : true; + min_period : 0.143 ; + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_512x64_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_512x64_1rw_DATA; + direction : output; + max_capacitance : 0.0488; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_512x64_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_512x64_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_512x64_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + fall_transition(fakeram_512x64_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_512x64_1rw_ADDRESS; + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_512x64_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_512x64_1rw_WMASK; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/bp_processor/sram/lib/fakeram_512x8_1rw.lib b/designs/gt2n/bp_processor/sram/lib/fakeram_512x8_1rw.lib new file mode 100644 index 00000000..771b9c1f --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lib/fakeram_512x8_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_512x8_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-09-18 18:35:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_512x8_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_512x8_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_512x8_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_512x8_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_512x8_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_512x8_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x8_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x8_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_512x8_1rw) { + area : 592.426; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 8; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.00244; + clock : true; + min_period : 0.143 ; + internal_power(){ + rise_power(fakeram_512x8_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_512x8_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_512x8_1rw_DATA; + direction : output; + max_capacitance : 0.0488; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_512x8_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_512x8_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_512x8_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + fall_transition(fakeram_512x8_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_512x8_1rw_ADDRESS; + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_512x8_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_512x8_1rw_WMASK; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_512x8_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_512x8_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/bp_processor/sram/lib/fakeram_64x184_1rw.lib b/designs/gt2n/bp_processor/sram/lib/fakeram_64x184_1rw.lib new file mode 100644 index 00000000..b49c47ee --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lib/fakeram_64x184_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_64x184_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-09-18 18:35:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x184_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x184_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x184_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x184_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x184_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x184_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 184; + bit_from : 183; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x184_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x184_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 184; + bit_from : 183; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x184_1rw) { + area : 1695.557; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 184; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.00244; + clock : true; + min_period : 0.143 ; + internal_power(){ + rise_power(fakeram_64x184_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_64x184_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_64x184_1rw_DATA; + direction : output; + max_capacitance : 0.0488; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x184_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_64x184_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_64x184_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + fall_transition(fakeram_64x184_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_64x184_1rw_ADDRESS; + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_64x184_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_64x184_1rw_WMASK; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x184_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x184_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/gt2n/bp_processor/sram/lib/fakeram_64x50_1rw.lib b/designs/gt2n/bp_processor/sram/lib/fakeram_64x50_1rw.lib new file mode 100644 index 00000000..bd07255a --- /dev/null +++ b/designs/gt2n/bp_processor/sram/lib/fakeram_64x50_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_64x50_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-09-18 18:35:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.125; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x50_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x50_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x50_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x50_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x50_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x50_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 50; + bit_from : 49; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x50_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x50_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 50; + bit_from : 49; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x50_1rw) { + area : 462.757; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 50; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.00244; + clock : true; + min_period : 0.143 ; + internal_power(){ + rise_power(fakeram_64x50_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + fall_power(fakeram_64x50_1rw_energy_template_clkslew) { + index_1 ("0.005, 0.125"); + values ("1.000, 1.000") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_64x50_1rw_DATA; + direction : output; + max_capacitance : 0.0488; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x50_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + cell_fall(fakeram_64x50_1rw_mem_out_delay_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.000488, 0.0488"); + values ( \ + "0.200, 0.200", \ + "0.200, 0.200" \ + ) + } + rise_transition(fakeram_64x50_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + fall_transition(fakeram_64x50_1rw_mem_out_slew_template) { + index_1 ("0.000488, 0.0488"); + values ("0.005, 0.125") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_64x50_1rw_ADDRESS; + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_64x50_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_64x50_1rw_WMASK; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.000488; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + fall_constraint(fakeram_64x50_1rw_constraint_template) { + index_1 ("0.005, 0.125"); + index_2 ("0.005, 0.125"); + values ( \ + "0.007, 0.007", \ + "0.007, 0.007" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + fall_power(fakeram_64x50_1rw_energy_template_sigslew) { + index_1 ("0.005, 0.125"); + values ("0.010, 0.010") + } + } + } + cell_leakage_power : 100.000; +} + +} diff --git a/designs/src/bp_processor/DECISIONS.md b/designs/src/bp_processor/DECISIONS.md index 55405264..6433584f 100644 --- a/designs/src/bp_processor/DECISIONS.md +++ b/designs/src/bp_processor/DECISIONS.md @@ -113,3 +113,28 @@ existing config. (+6.1 %), power 523 mW. - **sky130hd**: 368 735 logic cells (+0.4 %), WNS **+3489 ps** (met; base +4144), Fmax 0.035 GHz (+15.1 %), power 488 mW. Detail route converged cleanly (1307 → 154 → 27 → 0 violations). + +## gt2n — bp_uno (2026-09-25) + +**Status**: finishing (not fully clean) +**Last updated**: 2026-09-25 + +### Configuration +- `CORE_UTILIZATION = 35` (`PLACE_DENSITY = 0.42`) — auto-sized via `CORE_UTILIZATION`, unlike the + fixed `DIE_AREA` every other bp_uno port needed. RTLMP auto-placement handles the macros here with + no hand-placed grid (unlike bp_uno-sky130hd / NVDLA partition_c-gt2n). +- `MAX_ROUTING_LAYER = M11`, `MIN_CLK_ROUTING_LAYER = M4` — `M6` (NVDLA partition_c's macro-heavy + recommendation) was tried and made zero measurable difference; reverted to `M4`. +- Clock: `4628 ps` (Fmax 216.1 MHz, `period_min` 4620 ps) +- No `SKIP_INCREMENTAL_REPAIR` — unlike asap7/nangate45, gt2n needs incremental repair enabled to + close (matches the snitch_cluster-gt2n finding); skipping it left 671 setup + 2329 hold violations. + +### Decisions +- **2026-09-25**: initial gt2n port. Setup nearly closes (WNS -16.84 ps, 1 violation). Hold + violations remained irrespective of loosening/tightening the clock period. `HOLD_SLACK_MARGIN` + was tried and reduced hold violations but severely impacted setup timing (WNS to -572.83 ps); + not used. + +### Known issues / open questions +- Not fully clean: 1 setup violation (-16.84 ps), 17 hold violations (worst -9.06 ps). Root cause + not isolated — further closure may need investigation beyond SDC/margin knobs. diff --git a/designs/src/bp_processor/dev/gen_macros_v.py b/designs/src/bp_processor/dev/gen_macros_v.py index d4caf773..9947fb49 100755 --- a/designs/src/bp_processor/dev/gen_macros_v.py +++ b/designs/src/bp_processor/dev/gen_macros_v.py @@ -50,6 +50,7 @@ "designs/asap7/bp_processor", "designs/nangate45/bp_processor", "designs/sky130hd/bp_processor", + "designs/gt2n/bp_processor", ] diff --git a/designs/src/bp_processor/dev/generated/fakeram_gt2n.cfg b/designs/src/bp_processor/dev/generated/fakeram_gt2n.cfg new file mode 100644 index 00000000..bfa224df --- /dev/null +++ b/designs/src/bp_processor/dev/generated/fakeram_gt2n.cfg @@ -0,0 +1,26 @@ +{ + "tech_nm": 2, + "voltage": 0.7, + "metalPrefix": "M", + + "LRpinWidth_nm": 12, + "LRpinPitch_nm": 24, + "LRpinLayer": "M2", + + "TBpinWidth_nm": 14, + "TBpinPitch_nm": 28, + "TBpinLayer": "M3", + + "flipPins": false, + "snapWidth_nm": 42, + "snapHeight_nm": 144, + + "srams": [ + { "name": "fakeram_512x64_1rw", "width": 64, "depth": 512, "banks": 1, "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1} }, + { "name": "fakeram_64x184_1rw", "width": 184, "depth": 64, "banks": 1, "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1} }, + { "name": "fakeram_512x8_1rw", "width": 8, "depth": 512, "banks": 1, "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1} }, + { "name": "fakeram_64x50_1rw", "width": 50, "depth": 64, "banks": 1, "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1} }, + { "name": "fakeram_32x48_1rw", "width": 48, "depth": 32, "banks": 1, "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1} }, + { "name": "fakeram_128x8_1rw", "width": 8, "depth": 128, "banks": 1, "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1} } + ] +}