diff --git a/REUSE.toml b/REUSE.toml
index 309f2a9..044aa7f 100644
--- a/REUSE.toml
+++ b/REUSE.toml
@@ -29,3 +29,8 @@ SPDX-License-Identifier = "CERN-OHL-S-2.0"
 [[annotations]]
 path = "hardware/LICENSE"
 SPDX-License-Identifier = "CERN-OHL-S-2.0"
+
+[[annotations]]
+path = "hardware/boards/compact-carrier-board/**"
+SPDX-FileCopyrightText = "2026 Jon Truland"
+SPDX-License-Identifier = "CERN-OHL-S-2.0"
diff --git a/hardware/boards/compact-carrier-board/README.md b/hardware/boards/compact-carrier-board/README.md
new file mode 100644
index 0000000..c9241ef
--- /dev/null
+++ b/hardware/boards/compact-carrier-board/README.md
@@ -0,0 +1,234 @@
+# compact-carrier-board
+
+Small distribution PCB that sits under the ESP32-C3-Zero where it mounts through
+the desk's ESP slot, fanning its I2C/I2S/power pins out to the PCA9685, OLED,
+MAX98357A amp, and servo power — instead of point-to-point wiring.
+
+- **Status:** in review
+- **KiCad:** 10
+- **Interfaces:** ESP32-C3-Zero 2×9 socket, `J_PWR` (5V/GND + external USB
+  D+/D-), `J_SERVO`, `J_I2C_OLED`, `J_I2C_PCA`, `J_I2S`
+- **Assumptions:** sized against the desk generated with the **PowerHD
+  HD-1370A** servo preset (`servos.json`) — the SG90 and FS0307 presets
+  produce different desk dimensions per the parametric design docs, and this
+  board's fit has **not** been verified against either of them. Re-check the
+  ESP slot dimensions in your own exported desk model before relying on this
+  outline if you're on a different preset. See `docs/hardware/interfaces.md`
+  for the canonical net map (5V/3.3V domains, GP0-GP4 assignments); this
+  board implements that map in copper.
+- **Built:** the `carrier-fab-v3-replacement_Y5` upload was produced and
+  shipped by JLCPCB (not yet received). That batch carries the **mirrored
+  socket map this revision fixes** — see "Mirrored socket map (boards in
+  transit)" below for the assembly workaround. Its drilling is fine: the Y5
+  drill export is a single 0.9mm tool over all 37 holes and JLC's own CAM
+  layer a single aperture, so the 7-undersized-hole defect of the earlier
+  `_Y3` upload never reached a physical board.
+
+## Files
+
+- `compact-carrier-board.kicad_pcb` — KiCad 10 board source
+- `compact-carrier-board.kicad_pro` — KiCad 10 project file (no `.kicad_sch`
+  — this board has no schematic, laid out directly from footprints)
+- `carrier-board-render.png` — 3D top render, regenerated with
+  `kicad-cli pcb render --side top` after the row swap and silk additions
+
+Gerbers, drill, BOM, and CPL are generated outputs, not source — regenerate
+them from `compact-carrier-board.kicad_pcb` when ordering rather than
+relying on a committed copy. `J_ESP1`/`J_ESP2` carry real `Value`/`LCSC`
+fields and each footprint has a real origin at its own center, so
+`kicad-cli pcb export pos` produces correct positions directly (verified:
+`(13.00, -16.89)` / `(13.00, -1.65)`) — no manual patching. `J_PWR`,
+`J_SERVO`, `J_I2C_OLED`, `J_I2C_PCA`, and `J_I2S` are flagged
+`exclude_from_bom`/`exclude_from_pos_files` so they never appear in either
+export. There's no `.kicad_sch`, so `kicad-cli` has no BOM-export
+subcommand for this board (that's a schematic-only feature) — a BOM script
+or fab-tool plugin reading the `.kicad_pcb`'s footprint properties directly
+now gets correct `Value`/`LCSC` without hand-derivation.
+
+## Assembly: only the ESP header strips are populated parts
+
+`J_PWR`, `J_SERVO`, `J_I2C_OLED`, `J_I2C_PCA`, and `J_I2S` are bare
+through-holes for direct wire connections, not connector footprints to
+populate — excluded from BOM/CPL at the footprint level (see above).
+
+`J_ESP1`/`J_ESP2` are the one real part: **Kinghelm KH-2.54FH-1X9P-H3.5**
+(LCSC/JLCPCB `C55778388`), a 2.54mm 1×9 THT female header. There's no 2×9 part
+— the
+ESP32-C3-Zero's socket needs **two** of these strips, one per row. The board
+models this as two separate footprint objects, **`J_ESP1`** (the inner row,
+nearer the wire end: 5V/GND/3V3/GPIO0-5) and **`J_ESP2`** (the outer row,
+nearest the slot edge: GPIO21-GPIO6), each a real
+9-pad object with its own designator — not one 2×9 footprint with a
+quantity hint in prose. JLCPCB's assembly tooling (and most BOM tooling)
+determines quantity by counting designators, not by parsing Comment text, so
+a generated BOM lists both on one row as `"J_ESP1,J_ESP2"` (identical part,
+JLC's own convention for grouping identical components) — that reads as qty
+2 unambiguously.
+
+A generated CPL has one row per designator, `J_ESP1` and `J_ESP2`, each at
+its own row's real center — (13.00, 16.89) and (13.00, 1.65) in the board's
+own coordinates — read directly by `kicad-cli pcb export pos` from each
+footprint's own origin, no hand-derivation needed.
+
+## Why this shape
+
+Measured directly from an exported desk part (not estimated): the ESP mounting
+slot is 25.0 × 18.5mm, and three of its four sides sit only 3.0–3.6mm from
+full-height enclosure walls — too tight for any connector housing. Only the
+front is open. That forced the layout:
+
+- **26 × 44mm**, 2-layer.
+- Back 18.5mm: 2×9 female socket for the ESP32-C3-Zero (2.54mm pitch,
+  15.24mm row spacing — Waveshare's documented spec for the Zero board family,
+  confirmed within 0.04mm of a direct caliper measurement).
+- Front zone: `J_PWR` (now 4-pin — 5V/GND plus the external USB D+/D-, see
+  below), `J_SERVO` (5V direct to PCA9685 V+, bypassing the ESP's own 3.3V
+  regulator), `J_I2C_OLED`, `J_I2C_PCA` (separate connectors, bus shared via
+  on-board copper — no external splitter cable), `J_I2S` (own on-board 5V
+  feed for the amp).
+- Everything routes fully on-board; nothing needs an off-board jumper.
+
+## Pinout (rows stated in the frame that decides them)
+
+Row placement is the part that is easy to get backwards, so name the rule:
+**the pad map, seen from the face the module plugs into, has to be the
+module's component-side view.** A pin-side view is the correct drawing only
+for a socket on the *opposite* face — that inversion is exactly what went
+wrong in the shipped batch (below).
+
+Hold the C3-Zero component side up with its USB-C over this board's 5V-bus
+edge (the long edge the 5V trace hugs). Then:
+
+- **Outer row** — `J_ESP2`, nearest the slot edge (y=14.15):
+  `GPIO21, GPIO20, GPIO19, GPIO18, GPIO10, GPIO9, GPIO8, GPIO7, GPIO6`.
+  Mechanical/no-net support **except GP19 and GP18**, the native USB pair —
+  see USB below.
+- **Inner row** — `J_ESP1`, nearer the wire end (y=29.39):
+  `5V, GND, 3V3, GPIO0(SDA), GPIO1(SCL), GPIO2(BCLK), GPIO3(LRCLK), GPIO4(DIN), GPIO5`
+
+Pins 1 and 18 land at the 5V-bus edge in both rows, and that is what fixes
+the module's USB-C to that edge. Traversing 1 to 18 reads counter-clockwise
+from above, matching Waveshare's own pinout art (1-9 down the left column,
+10-18 up the right, USB-C at the top).
+
+## USB pass-through (external jack, not the C3-Zero's own USB-C)
+
+Per `docs/hardware/interfaces.md`: the robot's single external USB-C (Adafruit
+5993) carries both power and the ESP32's native USB D+/D- lines, so flashing
+and serial CDC work through the panel-mount jack once the desk is sealed —
+the C3-Zero's own onboard USB-C is left unused. No ESD or series-resistor
+circuitry is specified for this link; it's a direct connection.
+
+| `J_PWR` pin | Net | Goes to |
+| --- | --- | --- |
+| 1 | GND | common ground |
+| 2 | D+ | ESP32 **GPIO19** (outer-row pad, native USB DP) |
+| 3 | D− | ESP32 **GPIO18** (outer-row pad, native USB DM) |
+| 4 | 5V | ESP32 5V rail, PCA9685 V+ (via `J_SERVO`), MAX98357A |
+
+D+/D- run down the same 2.54mm grid columns as their own pads (x=20.42 and
+22.96), which sits half a pitch off `J_I2C_OLED`/`J_I2C_PCA`'s grid, so they
+never cross those connectors' pads on the way past. Since the row swap they
+also pass the inner row, where the 3V3 and SDA holes occupy those two
+columns, so each line takes one short lateral jog into the adjacent lane
+(1.27mm off-axis, 0.42mm to the nearest pad edge) and returns — still F.Cu,
+no vias. Each line measures 36.088mm and the two are exactly length-matched;
+that is 16mm longer than before the swap, which is electrically unremarkable
+at full-speed 12 Mbps.
+
+## Mirrored socket map (boards in transit)
+
+That artwork is preserved as its own board, [`compact-carrier-board-pinside`](../compact-carrier-board-pinside/README.md),
+so the build the in-transit batch needs stays orderable and documented rather than
+living only in this section's prose.
+
+**The shipped boards (`carrier-fab-v3-replacement_Y5`) have the two socket
+rows the wrong way round.** Their pad map is the C3-Zero seen from its *pin
+side*, which is the correct drawing only for a socket on the opposite face;
+as fabricated, a component-side-up module does not mate.
+
+Caught by handedness, which no rotation can change: on the module
+(component side, USB-C up) pins 1-9 run DOWN the left column and 10-18 UP
+the right, so 1 to 18 is counter-clockwise; on those boards `J_ESP1` 1 to 9
+runs left-to-right along the outer row and `J_ESP2` 10 to 18 right-to-left
+along the inner row, i.e. clockwise.
+
+**This revision fixes the source** — rows swapped in copper, nothing moved
+mechanically. **For the boards in transit, fix it at assembly:** solder both
+female strips to the **pour face** (B.Cu) and run that face up. From the
+pour face you see the mirror of the F.Cu artwork, which is the
+component-side map, so the module mates. What that build costs: the module's
+own USB-C ends up over the long edge facing the opposite wall from this
+revision's intent (unused either way — the Adafruit 5993 jack carries power
+and CDC), the silkscreen ends up underneath so mark pin 1 before assembly,
+and the wire-end connector positions mirror left-right, so the runs to the
+PCA9685 / OLED / amp swap sides.
+
+## Fab notes
+
+- `kicad-cli pcb drc --severity-all` (KiCad 10.0.6, run *without*
+  `--refill-zones` so it judges the on-disk fill) reports **0 violations and
+  0 unconnected items** — and that statement now means something. The
+  project's DRC floors used to be `min_clearance` 0.0, `min_silk_clearance`
+  0.0, `min_text_height` 0.8 and `min_text_thickness` 0.08, so DRC could not
+  have failed on clearance, silk overlap or undersized text however bad they
+  got. They are now 0.2 / 0.15 / 1.0 / 0.15, matching JLCPCB's floors and
+  its standard-font minimum. Schematic parity is not checked and cannot be —
+  there is no `.kicad_sch` for this board, and `--schematic-parity` answers
+  "Schematic parity tests require a fully annotated schematic".
+- **Every pad on the board is named on silk.** The socket rows carry
+  `GP21`-`GP6` (outer) and `5V, GND, 3V3, GP0`-`GP5` (inner) with a `USB`
+  arrow pointing at the 5V-bus edge; each wire-end connector carries its own
+  pin names (`3V3/SDA/SCL/GND` on both I2C headers, `5V/BCLK/LRC/DIN/GND` on
+  `J_I2S`, `GND/D+/D-/5V` on `J_PWR`, `5V/GND` on `J_SERVO`). 48 silk items,
+  all 1.0mm height / 0.15mm stroke. Placement is checked geometrically, not
+  by DRC — 0 silk-to-silk overlaps, 0.421mm minimum silk-to-pad, 0.383mm
+  minimum silk-to-edge. Before this the board carried nothing but seven
+  reference designators, which is why a mirrored pad map was invisible both
+  in the render and on the bare board.
+- The seven reference designators were 0.8mm high with a 0.12mm stroke,
+  under JLCPCB's standard-font minimum and passing DRC only because
+  `min_text_thickness` was 0.08. All seven are now 1.0mm / 0.15mm.
+  `J_I2C_PCA`, `J_PWR` and `J_SERVO` moved to clear the new pin-name bands,
+  and every label is re-checked against the 0.30mm edge margin — three of
+  them sit at exactly that margin, so the larger text boxes were nudged back
+  inside rather than allowed to overhang.
+- GND pour clearance raised 0.20 → 0.25mm — the zone's local clearance and
+  the Default netclass together — and refilled. At 0.20 the fill sat at
+  exactly JLCPCB's floor with nothing left for their etch tolerance; the
+  nearest track-based constraint is 0.42mm, so the extra 0.05mm costs no
+  geometry.
+- 4 reference designators (`J_ESP1`, `J_ESP2`, `J_I2C_OLED`, `J_I2C_PCA`)
+  were printing 0.2–0.6mm past the board's left edge — visually confirmed,
+  not just a DRC technicality. Each footprint's own text bounding box (not
+  an estimate) was used to shift the label right just enough to sit at a
+  0.3mm margin from the edge; the render below reflects the fix.
+- GND zone (B.Cu) outline is inset 0.5mm from the board edge, not 1mm as in
+  earlier revisions — the 1mm inset put pads near the top edge (e.g. `J_ESP1`
+  pin 2, GND) close enough to the zone's own boundary that a fresh zone
+  refill could fail to route a thermal-relief connection to them, especially
+  after the `J_ESP2` drill fix changed nearby pad geometry. Swept the inset
+  from 1.0mm down to 0.3mm in 8 steps against the drill-fixed board, each
+  with a fresh `kicad-cli pcb drc --refill-zones`: 1.0mm and 0.8mm both
+  reproducibly fail with 1 unconnected pad; every value from 0.6mm down to
+  0.3mm passes with 0. 0.5mm sits in the middle of that verified-safe range
+  — well clear of the failure boundary and with real margin above JLCPCB's
+  ~0.2–0.3mm copper-to-edge floor.
+- Tightest feature: 0.15mm copper (GND pour minimum thickness). Comfortably
+  inside JLCPCB's 0.127mm floor; sits exactly at PCBWave's 0.15mm floor (their
+  recommended safe minimum is 0.20mm) — check their DFM report before ordering
+  if using PCBWave.
+- Connectors are plain 2.54mm through-hole pads (pin headers + jumpers), not
+  JST — real JST-PH footprint dimensions weren't verified at design time.
+- 5V trace sized per IPC-2221 (2A, 1oz copper, 10°C rise → ≈0.78mm minimum).
+  The whole net is now 1.0mm over its 44.9mm length, with **no pinch points
+  left**: the row swap moved the 5V pad off the outer row onto the inner one,
+  15.24mm closer to its loads, which removed the squeeze past the mechanical
+  pad row that previously forced two short 0.6mm sections.
+  Any track change requires refilling the GND zone, and the refill must be
+  done via KiCad itself (GUI Fill All Zones + save, or the
+  `pcbnew.ZONE_FILLER` Python API) and re-verified with `kicad-cli pcb drc`
+  run *without* `--refill-zones` — that flag only recomputes the fill
+  in-memory for the check, it does not persist to the file, so a stale
+  on-disk fill can pass DRC while still being wrong in the Gerbers. This bit
+  us once already in this revision's history.
diff --git a/hardware/boards/compact-carrier-board/carrier-board-render.png b/hardware/boards/compact-carrier-board/carrier-board-render.png
new file mode 100644
index 0000000..1cd553f
Binary files /dev/null and b/hardware/boards/compact-carrier-board/carrier-board-render.png differ
diff --git a/hardware/boards/compact-carrier-board/compact-carrier-board.kicad_pcb b/hardware/boards/compact-carrier-board/compact-carrier-board.kicad_pcb
new file mode 100644
index 0000000..cd830a7
--- /dev/null
+++ b/hardware/boards/compact-carrier-board/compact-carrier-board.kicad_pcb
@@ -0,0 +1,2021 @@
+(kicad_pcb
+	(version 20260206)
+	(generator "pcbnew")
+	(generator_version "10.0")
+	(general
+		(thickness 1.6)
+		(legacy_teardrops no)
+	)
+	(paper "A4")
+	(layers
+		(0 "F.Cu" signal)
+		(2 "B.Cu" signal)
+		(9 "F.Adhes" user "F.Adhesive")
+		(11 "B.Adhes" user "B.Adhesive")
+		(13 "F.Paste" user)
+		(15 "B.Paste" user)
+		(5 "F.SilkS" user "F.Silkscreen")
+		(7 "B.SilkS" user "B.Silkscreen")
+		(1 "F.Mask" user)
+		(3 "B.Mask" user)
+		(17 "Dwgs.User" user "User.Drawings")
+		(19 "Cmts.User" user "User.Comments")
+		(25 "Edge.Cuts" user)
+		(27 "Margin" user)
+		(31 "F.CrtYd" user "F.Courtyard")
+		(29 "B.CrtYd" user "B.Courtyard")
+		(35 "F.Fab" user)
+		(33 "B.Fab" user)
+	)
+	(setup
+		(pad_to_mask_clearance 0)
+		(allow_soldermask_bridges_in_footprints no)
+		(tenting
+			(front yes)
+			(back yes)
+		)
+		(covering
+			(front no)
+			(back no)
+		)
+		(plugging
+			(front no)
+			(back no)
+		)
+		(capping no)
+		(filling no)
+		(pcbplotparams
+			(layerselection 0x00000000_00000000_55555555_5755f5ff)
+			(plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000)
+			(disableapertmacros no)
+			(usegerberextensions no)
+			(usegerberattributes yes)
+			(usegerberadvancedattributes yes)
+			(creategerberjobfile yes)
+			(dashed_line_dash_ratio 12)
+			(dashed_line_gap_ratio 3)
+			(svgprecision 4)
+			(plotframeref no)
+			(mode 1)
+			(useauxorigin no)
+			(pdf_front_fp_property_popups yes)
+			(pdf_back_fp_property_popups yes)
+			(pdf_metadata yes)
+			(pdf_single_document no)
+			(dxfpolygonmode yes)
+			(dxfimperialunits yes)
+			(dxfusepcbnewfont yes)
+			(psnegative no)
+			(psa4output no)
+			(plot_black_and_white yes)
+			(sketchpadsonfab no)
+			(plotpadnumbers no)
+			(hidednponfab no)
+			(sketchdnponfab yes)
+			(crossoutdnponfab yes)
+			(subtractmaskfromsilk no)
+			(outputformat 1)
+			(mirror no)
+			(drillshape 1)
+			(scaleselection 1)
+			(outputdirectory "")
+		)
+	)
+	(footprint "J_ESP1"
+		(layer "F.Cu")
+		(uuid "00f35c3b-1d3b-49b1-83b3-528f4b5a8326")
+		(at 25.5 29.39)
+		(property "Reference" "J_ESP1"
+			(at -7.62 2.2 0)
+			(layer "F.SilkS")
+			(uuid "645db12c-9084-42e4-8d93-f785e71c7981")
+			(effects
+				(font
+					(size 1 0.75)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "Kinghelm KH-2.54FH-1X9P-H3.5"
+			(at -13 -1.65 0)
+			(layer "F.Fab")
+			(uuid "6f4a6c70-dd7e-4c5e-8a49-9f688cf7557b")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at -13 -1.65 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "842a872f-cf9a-42e9-adff-6dfca7a69fd1")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" ""
+			(at -13 -1.65 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "5bac8db0-d495-4acc-b100-785c8b21fbd4")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "LCSC" "C55778388"
+			(at 0 0 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "a273c7a1-1a02-4473-84da-68f47a08b89f")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+			)
+		)
+		(attr through_hole)
+		(duplicate_pad_numbers_are_jumpers no)
+		(pad "1" thru_hole rect
+			(at -10.16 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "5V")
+			(uuid "406ab857-e308-4e47-8d3e-128e2dab41da")
+		)
+		(pad "2" thru_hole circle
+			(at -7.62 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "GND")
+			(zone_connect 3)
+			(uuid "6820b12d-5bf2-4d74-bd38-bf9cb2eb1000")
+		)
+		(pad "3" thru_hole circle
+			(at -5.08 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "3V3")
+			(uuid "031ab41e-ae56-4334-b01b-0821a4f4015a")
+		)
+		(pad "4" thru_hole circle
+			(at -2.54 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "SDA")
+			(uuid "ef9e1b43-a44a-446c-9ab4-fc9d2f6a2168")
+		)
+		(pad "5" thru_hole circle
+			(at 0 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "SCL")
+			(uuid "5b1794c1-1efb-4f3a-927e-1e4b3c6385bb")
+		)
+		(pad "6" thru_hole circle
+			(at 2.54 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "BCLK")
+			(uuid "b5bc0754-0670-424f-85e6-2506ad4d1b5e")
+		)
+		(pad "7" thru_hole circle
+			(at 5.08 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "LRCLK")
+			(uuid "6b7ed294-2044-428d-bedb-21fcf44dfa7a")
+		)
+		(pad "8" thru_hole circle
+			(at 7.62 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "DIN")
+			(uuid "c0596cb8-bae6-4a6a-b17f-6fe2866b7051")
+		)
+		(pad "9" thru_hole circle
+			(at 10.16 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "a653168c-b711-4209-822c-db3581b24272")
+		)
+		(embedded_fonts no)
+	)
+	(footprint "J_I2C_PCA"
+		(layer "F.Cu")
+		(uuid "02bab699-d536-4f1b-a4bc-33a7c9393519")
+		(at 20.42 42.5)
+		(property "Reference" "J_I2C_PCA"
+			(at 10.58 0 0)
+			(layer "F.SilkS")
+			(uuid "181638da-4053-4d37-93ed-2f2453f104f8")
+			(effects
+				(font
+					(size 1 0.75)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" ""
+			(at -7.92 -30 0)
+			(layer "F.Fab")
+			(uuid "d63071c6-e3d6-4cc3-ac63-bddb81b802e0")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at -7.92 -30 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "dddd774f-59aa-4978-829b-aa502e0c6bde")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" ""
+			(at -7.92 -30 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "a4d47860-c30f-4f07-9765-489eff585d6b")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(attr through_hole exclude_from_pos_files exclude_from_bom)
+		(duplicate_pad_numbers_are_jumpers no)
+		(pad "1" thru_hole rect
+			(at -3.81 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "3V3")
+			(uuid "3ea1ea2a-1652-4625-83fb-5ea2c0f2a043")
+		)
+		(pad "2" thru_hole circle
+			(at -1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "SDA")
+			(uuid "009425aa-b676-41a7-99b3-bdd7de54787a")
+		)
+		(pad "3" thru_hole circle
+			(at 1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "SCL")
+			(uuid "eb3b3968-a654-42a0-a796-6921969024a0")
+		)
+		(pad "4" thru_hole circle
+			(at 3.81 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "GND")
+			(uuid "ac094091-9898-4d85-bd15-857a63694acb")
+		)
+		(embedded_fonts no)
+	)
+	(footprint "J_I2C_OLED"
+		(layer "F.Cu")
+		(uuid "2d5e32c0-494a-4ba6-b3ea-366d67009cd6")
+		(at 20.42 36.5)
+		(property "Reference" "J_I2C_OLED"
+			(at -4.129524 -2 0)
+			(layer "F.SilkS")
+			(uuid "1d461778-e48d-4eaa-900d-6641cdbb8440")
+			(effects
+				(font
+					(size 1 0.75)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" ""
+			(at -7.92 -24 0)
+			(layer "F.Fab")
+			(uuid "ae6bff0b-d600-431c-8ec8-8805214999a9")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at -7.92 -24 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "10277f74-3373-48c4-9ed5-e982d9dd5fb4")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" ""
+			(at -7.92 -24 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "2e11dbaa-9d7b-4308-a3f1-87f3f010b6af")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(attr through_hole exclude_from_pos_files exclude_from_bom)
+		(duplicate_pad_numbers_are_jumpers no)
+		(pad "1" thru_hole rect
+			(at -3.81 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "3V3")
+			(uuid "63a9d440-f031-4d76-9547-1d4efb719f47")
+		)
+		(pad "2" thru_hole circle
+			(at -1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "SDA")
+			(uuid "5e205820-38d6-41e5-891f-2e9189529841")
+		)
+		(pad "3" thru_hole circle
+			(at 1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "SCL")
+			(uuid "7678e93d-1160-42fc-a688-9e8ca8afedea")
+		)
+		(pad "4" thru_hole circle
+			(at 3.81 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "GND")
+			(uuid "db83b625-be30-433c-8d53-40f6bb337f2f")
+		)
+		(embedded_fonts no)
+	)
+	(footprint "J_PWR"
+		(layer "F.Cu")
+		(uuid "e1d533b4-8528-4ce6-84b9-0f164bffbc47")
+		(at 21.69 49.5)
+		(property "Reference" "J_PWR"
+			(at -2.69 5.5 0)
+			(layer "F.SilkS")
+			(uuid "045b660b-badd-45cc-a1d8-f78257aa4143")
+			(effects
+				(font
+					(size 1 0.75)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" ""
+			(at -9.19 -37 0)
+			(layer "F.Fab")
+			(uuid "41255245-8281-4e44-886a-ed16a65bc5d1")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at -9.19 -37 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "e3541459-6c35-4cbd-a8c6-536764a64c02")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" ""
+			(at -9.19 -37 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "05049e8c-9954-48c7-8649-f555fc23d3e7")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(attr through_hole exclude_from_pos_files exclude_from_bom)
+		(duplicate_pad_numbers_are_jumpers no)
+		(pad "1" thru_hole rect
+			(at -3.81 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "GND")
+			(uuid "314e2252-9311-4707-a089-4231863e8f04")
+		)
+		(pad "2" thru_hole circle
+			(at -1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "USB_DP")
+			(uuid "dbef363f-4b5b-4d92-a9ad-44a4aacf44d9")
+		)
+		(pad "3" thru_hole circle
+			(at 1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "USB_DM")
+			(uuid "497c17b0-763c-41c0-9f1f-d9d923dcd21d")
+		)
+		(pad "4" thru_hole circle
+			(at 3.81 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "5V")
+			(uuid "8982da9d-82b4-45ab-b30e-d6c569024630")
+		)
+		(embedded_fonts no)
+	)
+	(footprint "J_I2S"
+		(layer "F.Cu")
+		(uuid "e346a8d7-3e3b-4482-bc03-e987f4eb5394")
+		(at 31.85 36.5)
+		(property "Reference" "J_I2S"
+			(at -6.28 -2 0)
+			(layer "F.SilkS")
+			(uuid "d84bc25c-8a64-4f88-b328-6a4b4f58c609")
+			(effects
+				(font
+					(size 1 0.75)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" ""
+			(at -19.35 -24 0)
+			(layer "F.Fab")
+			(uuid "13da65db-a5cc-440b-b82c-b53fb04966bd")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at -19.35 -24 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "f120da44-c15c-43a2-a00a-4676b6f87b87")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" ""
+			(at -19.35 -24 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "00d5f2a9-e146-4918-8fea-638854674632")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(attr through_hole exclude_from_pos_files exclude_from_bom)
+		(duplicate_pad_numbers_are_jumpers no)
+		(pad "1" thru_hole rect
+			(at -5.08 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "5V")
+			(uuid "31e6006e-7aa9-4627-b01b-1b8b5174aed4")
+		)
+		(pad "2" thru_hole circle
+			(at -2.54 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "BCLK")
+			(uuid "6fee0eee-524e-4aac-aa42-a2de8853523b")
+		)
+		(pad "3" thru_hole circle
+			(at 0 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "LRCLK")
+			(uuid "8be88ebc-27c7-45ea-969a-ac775208b679")
+		)
+		(pad "4" thru_hole circle
+			(at 2.54 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "DIN")
+			(uuid "a4f39a26-b3d1-43ac-bdd4-0bd8d37abc04")
+		)
+		(pad "5" thru_hole circle
+			(at 5.08 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "GND")
+			(uuid "bc179dfd-1db4-4e12-b12a-9997748cd220")
+		)
+		(embedded_fonts no)
+	)
+	(footprint "J_ESP2"
+		(layer "F.Cu")
+		(uuid "e4eab69d-915b-4016-9895-2ad91432c873")
+		(at 25.5 14.15)
+		(property "Reference" "J_ESP2"
+			(at -10.466666 2.2 0)
+			(layer "F.SilkS")
+			(uuid "a31ad772-cb8b-4c47-9dad-4bde818da8c3")
+			(effects
+				(font
+					(size 1 0.75)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "Kinghelm KH-2.54FH-1X9P-H3.5"
+			(at -13 -16.89 0)
+			(layer "F.Fab")
+			(uuid "b7cd21d5-70b0-49f2-b2e2-cffa1bd5149c")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at -13 -16.89 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "912c9237-f99b-424f-ac6f-c412d18e9809")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" ""
+			(at -13 -16.89 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "3b8f6360-57d1-4087-9529-28f014caadff")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "LCSC" "C55778388"
+			(at 0 0 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "7e2ee078-ffc9-4a42-9864-b227f2841bbe")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+			)
+		)
+		(attr through_hole)
+		(duplicate_pad_numbers_are_jumpers no)
+		(pad "10" thru_hole circle
+			(at 10.16 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "9596541d-7a9c-4ac8-a82c-25fd744b0a0b")
+		)
+		(pad "11" thru_hole circle
+			(at 7.62 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "74c66df9-6f76-4eeb-a3b1-d05d9f653e9b")
+		)
+		(pad "12" thru_hole circle
+			(at 5.08 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "862c43b2-8b4f-48f4-96c8-3ce35fa4aa19")
+		)
+		(pad "13" thru_hole circle
+			(at 2.54 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "bd25bbac-19cc-405d-90c7-6117579ebe7e")
+		)
+		(pad "14" thru_hole circle
+			(at 0 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "aa4ecff6-deed-49a5-b66d-99ec1920d190")
+		)
+		(pad "15" thru_hole circle
+			(at -2.54 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "USB_DM")
+			(uuid "7ca438a9-46a5-4de2-962c-bed156077cca")
+		)
+		(pad "16" thru_hole circle
+			(at -5.08 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "USB_DP")
+			(uuid "587d71b6-23c3-49e5-8967-6ae89aa4c497")
+		)
+		(pad "17" thru_hole circle
+			(at -7.62 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "ef99bf86-3ed4-4bb4-8962-dae1ac55982c")
+		)
+		(pad "18" thru_hole circle
+			(at -10.16 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(uuid "3e9e294e-e66e-43ad-99d7-0a0a63ef8674")
+		)
+		(embedded_fonts no)
+	)
+	(footprint "J_SERVO"
+		(layer "F.Cu")
+		(uuid "e9528f6c-21fe-40dd-bea5-0a96bd12c4fc")
+		(at 29.31 49.5)
+		(property "Reference" "J_SERVO"
+			(at -0.01 5.5 0)
+			(layer "F.SilkS")
+			(uuid "feb32aa5-5711-4680-a1a1-3ff68895f43b")
+			(effects
+				(font
+					(size 1 0.75)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" ""
+			(at -16.81 -37 0)
+			(layer "F.Fab")
+			(uuid "64ea512c-11d5-4183-aa18-eebf404b33f3")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at -16.81 -37 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "f773be29-7e4f-4db0-9de0-91f4de5ec9c2")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" ""
+			(at -16.81 -37 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "9f50e171-8e2d-4749-8936-c7af1718a90d")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(attr through_hole exclude_from_pos_files exclude_from_bom)
+		(duplicate_pad_numbers_are_jumpers no)
+		(pad "1" thru_hole rect
+			(at -1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "5V")
+			(uuid "e7f16fdd-67a5-46af-b446-47d2b18c262f")
+		)
+		(pad "2" thru_hole circle
+			(at 1.27 0)
+			(size 1.4 1.4)
+			(drill 0.9)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net "GND")
+			(uuid "1ece2a29-a734-4322-93f4-4d619fd83ecb")
+		)
+		(embedded_fonts no)
+	)
+	(gr_line
+		(start 14.5 22)
+		(end 13.7 22.6)
+		(stroke
+			(width 0.15)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "23a4ca21-c3b1-4447-9d46-ab4f92903989")
+	)
+	(gr_line
+		(start 14.5 23.2)
+		(end 13.7 22.6)
+		(stroke
+			(width 0.15)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "034f1ddd-65be-4b6d-be4f-9568bb3a6241")
+	)
+	(gr_line
+		(start 16.5 22.6)
+		(end 13.7 22.6)
+		(stroke
+			(width 0.15)
+			(type default)
+		)
+		(layer "F.SilkS")
+		(uuid "6811117c-a77b-41db-b0fc-2b425ee592ee")
+	)
+	(gr_rect
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diff --git a/hardware/boards/compact-carrier-board/compact-carrier-board.kicad_pro b/hardware/boards/compact-carrier-board/compact-carrier-board.kicad_pro
new file mode 100644
index 0000000..b8f2687
--- /dev/null
+++ b/hardware/boards/compact-carrier-board/compact-carrier-board.kicad_pro
@@ -0,0 +1,330 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "apply_defaults_to_fp_barcodes": false,
+        "apply_defaults_to_fp_dimensions": false,
+        "apply_defaults_to_fp_fields": false,
+        "apply_defaults_to_fp_shapes": false,
+        "apply_defaults_to_fp_text": false,
+        "board_outline_line_width": 0.05,
+        "copper_line_width": 0.2,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.05,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": true,
+          "text_position": 0,
+          "units_format": 0
+        },
+        "fab_line_width": 0.1,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.1,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.8,
+          "height": 1.27,
+          "width": 1.27
+        },
+        "silk_line_width": 0.1,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.1,
+        "silk_text_upright": false,
+        "zones": {
+          "border_display_style": 2,
+          "border_hatch_pitch": 0.5,
+          "corner_radius": 0.0,
+          "corner_smoothing": 0,
+          "fill_mode": 0,
+          "hatch_gap": 1.5,
+          "hatch_orientation": 0.0,
+          "hatch_smoothing_level": 0,
+          "hatch_smoothing_value": 0.1,
+          "hatch_thickness": 1.0,
+          "min_clearance": 0.5,
+          "min_island_area": 10.0,
+          "min_thickness": 0.25,
+          "pad_connection": 1,
+          "remove_islands": 0,
+          "thermal_relief_gap": 0.5,
+          "thermal_relief_spoke_width": 0.5
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "creepage": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_filters_mismatch": "ignore",
+        "footprint_symbol_field_mismatch": "warning",
+        "footprint_symbol_mismatch": "warning",
+        "footprint_type_mismatch": "ignore",
+        "hole_clearance": "error",
+        "hole_to_hole": "warning",
+        "holes_co_located": "warning",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "mirrored_text_on_front_layer": "warning",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "missing_tuning_profile": "warning",
+        "net_conflict": "warning",
+        "nonmirrored_text_on_back_layer": "warning",
+        "npth_inside_courtyard": "error",
+        "padstack": "warning",
+        "pth_inside_courtyard": "error",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_on_edge_cuts": "error",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_angle": "error",
+        "track_dangling": "warning",
+        "track_not_centered_on_via": "ignore",
+        "track_on_post_machined_layer": "error",
+        "track_segment_length": "error",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "tuning_profile_track_geometries": "ignore",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "max_error": 0.005,
+        "min_clearance": 0.2,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.5,
+        "min_groove_width": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.2,
+        "min_microvia_drill": 0.1,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.15,
+        "min_text_height": 1.0,
+        "min_text_thickness": 0.15,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.2,
+        "min_via_annular_width": 0.1,
+        "min_via_diameter": 0.5,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_onpthpad": true,
+          "td_onroundshapesonly": false,
+          "td_onsmdpad": true,
+          "td_ontrackend": false,
+          "td_onvia": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_on_pad_in_zone": false,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [],
+      "tuning_pattern_settings": {
+        "diff_pair_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 1.0
+        },
+        "diff_pair_skew_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        },
+        "single_track_defaults": {
+          "corner_radius_percentage": 80,
+          "corner_style": 1,
+          "max_amplitude": 1.0,
+          "min_amplitude": 0.2,
+          "single_sided": false,
+          "spacing": 0.6
+        }
+      },
+      "via_dimensions": [],
+      "zones_allow_external_fillets": false
+    },
+    "ipc2581": {
+      "bom_rev": "",
+      "dist": "",
+      "distpn": "",
+      "internal_id": "",
+      "mfg": "",
+      "mpn": "",
+      "sch_revision": ""
+    },
+    "layer_pairs": [],
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "component_class_settings": {
+    "assignments": [],
+    "meta": {
+      "version": 0
+    },
+    "sheet_component_classes": {
+      "enabled": false
+    }
+  },
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "compact-carrier-board.kicad_pro",
+    "version": 3
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.25,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 2147483647,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.2,
+        "tuning_profile": "",
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 5
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "idf": "",
+      "netlist": "",
+      "plot": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "bus_aliases": {},
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "top_level_sheets": [
+      {
+        "filename": "compact-carrier-board.kicad_sch",
+        "name": "compact-carrier-board",
+        "uuid": "00000000-0000-0000-0000-000000000000"
+      }
+    ]
+  },
+  "sheets": [],
+  "text_variables": {},
+  "tuning_profiles": {
+    "meta": {
+      "version": 0
+    },
+    "tuning_profiles_impedance_geometric": []
+  }
+}