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| 1 | +--- |
| 2 | +title: Microchip Laguna Support |
| 3 | +author: troglobit |
| 4 | +date: 2026-09-25 10:00:00 +0200 |
| 5 | +categories: [showcase] |
| 6 | +tags: [boards] |
| 7 | +image: |
| 8 | + path: /assets/img/laguna-evb.png |
| 9 | + alt: Microchip EV23X71A (Laguna) evaluation board |
| 10 | + show_in_post: false |
| 11 | +--- |
| 12 | + |
| 13 | +Twenty-eight ports, one lonely Cortex-A53, and a switch core that does TSN + |
| 14 | +FRER and HSR/PRP in hardware. Say hello to Microchip *Laguna*, the LAN969x |
| 15 | +family, now supported in Infix via the [EV23X71A][1] evaluation board! |
| 16 | + |
| 17 | +{: #fig1} |
| 18 | +_**Figure 1**: Microchip EV23X71A, a.k.a. the Laguna EVB. Twenty-four RJ45s |
| 19 | +and four SFP+ cages along the bottom edge._ |
| 20 | + |
| 21 | +### Hardware |
| 22 | + |
| 23 | +The EVB is a big, green, no-nonsense board built around a LAN9696RED, the 60 |
| 24 | +Gbps member of the family, where *RED* stands for hardware RedBox support |
| 25 | +(HSR/PRP). As eval boards usually go, Microchip have crammed all the things |
| 26 | +into this one, but the SoC comes in [many variants][6]. Common to all of them |
| 27 | +is the built-in single Cortex-A53 @ 1 GHz. The EVB also has 1 GiB DDR4, 4 GiB |
| 28 | +eMMC, and 2 MiB QSPI NOR flash. The latter is interesting if you want to try |
| 29 | +out Microchip's [VelocityDRIVE][7], have a look at it! |
| 30 | + |
| 31 | +The many ports are what you came for: |
| 32 | + |
| 33 | +- 24 x 1 GbE copper, six QSGMII quad PHYs in a neat row |
| 34 | +- 4 x 10 GbE SFP+ |
| 35 | +- 1 x 1 GbE RGMII management port |
| 36 | + |
| 37 | +It is the smaller sibling of the [SparX-5i][2], and the same Linux `sparx5` |
| 38 | +switchdev driver takes care of both, so everything you already know about |
| 39 | +bridging and VLANs in Infix works just as expected, all fully offloaded to the |
| 40 | +switch core, no CPU cycles involved. |
| 41 | + |
| 42 | +### Support Status |
| 43 | + |
| 44 | +The EVB starts out as Tier 3 in Infix, keeping the SparX-5i company. That |
| 45 | +sounds modest, and it is, but only because an evaluation board rarely ends |
| 46 | +up in a rack. What works today: |
| 47 | + |
| 48 | +- switch core and SerDes, all 29 ports, with switchdev offload |
| 49 | +- eMMC, I²C (including the SFP mux), SPI, and USB host |
| 50 | +- watchdog, temperature sensor, status and SFP LEDs |
| 51 | +- our own boot chain, from BL2 all the way to an A/B slot on the eMMC |
| 52 | + |
| 53 | +That last bullet deserves a moment. The U-Boot the board ships with cannot |
| 54 | +boot Infix from eMMC, so we built our own FIP (Trusted Firmware + U-Boot) |
| 55 | +from Microchip's trees. Along the way we tripped over a boot ROM erratum |
| 56 | +that made roughly one build in a hundred fail to authenticate, which was |
| 57 | +*great* fun to track down. The whole story is in the [board README][3]. |
| 58 | + |
| 59 | +Not there yet: TSN queueing (time aware shaping, PSFP) and HSR/PRP offload. |
| 60 | +The hardware is more than ready, it's our turn now. |
| 61 | + |
| 62 | +### Getting Started |
| 63 | + |
| 64 | +Laguna support ships with the upcoming v26.09 release, and until then in |
| 65 | +the [latest][4] builds. The bootloader is built with `laguna_boot_defconfig` |
| 66 | +and the rest is the standard aarch64 image, combined for eMMC using |
| 67 | +`utils/mkimage.sh`. The [board README][3] walks you through it all: |
| 68 | +boot mode strapping, installing the FIP, netbooting, and (just in case) |
| 69 | +debricking. |
| 70 | + |
| 71 | +### Coming Soon: Novarq Tactical-1000 |
| 72 | + |
| 73 | +Why all this effort on an EVB? Because it is the reference design for real |
| 74 | +products, and the first one is already on the bench. The [Novarq |
| 75 | +Tactical-1000][5] is basically a cut-down Laguna EVB in a box: same 24 + 4 + |
| 76 | +1 port layout, a LAN9696TSN, 2 GiB RAM, and a CPU fan that looks suspiciously |
| 77 | +like it was borrowed from a Raspberry Pi 5. |
| 78 | + |
| 79 | +{: #fig2} |
| 80 | +_**Figure 2**: Novarq Tactical-1000, the business end. Photo: Novarq._ |
| 81 | + |
| 82 | +This one is going straight to **Tier 1**, i.e., included in the default |
| 83 | +builds and tested in our regression test system. |
| 84 | +Stay tuned! |
| 85 | + |
| 86 | +[1]: https://www.microchip.com/en-us/development-tool/ev23x71a |
| 87 | +[2]: https://ww1.microchip.com/downloads/en/DeviceDoc/00002854B.pdf |
| 88 | +[3]: https://github.com/kernelkit/infix/tree/main/board/aarch64/microchip-ev23x71a |
| 89 | +[4]: https://github.com/kernelkit/infix/releases/tag/latest |
| 90 | +[5]: https://novarq.com/pages/tactical-1000 |
| 91 | +[6]: https://github.com/kernelkit/infix/tree/main/board/aarch64/microchip-ev23x71a#switch-core |
| 92 | +[7]: https://www.microchip.com/en-us/software-library/velocitydrive-sp |
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