From f27eb7bd0cacaeec0cb4100ac0e2085ce0a044d4 Mon Sep 17 00:00:00 2001 From: NobodyNo0ne Date: Thu, 27 Aug 2026 17:25:56 +0100 Subject: [PATCH 1/7] Squashed all commits Signed-off-by: NobodyNo0ne --- .circleci/config.yml | 30 +- .gitignore | 5 + blobs/xx80/README.md | 60 - blobs/xx80/hashes.txt | 5 + .../x280_download_clean_deguard_me_pad_tb.sh | 206 + blobs/xx80/x280_gbe.bin | Bin 0 -> 8192 bytes blobs/xx80/x280_ifd.bin | Bin 0 -> 4096 bytes .../EOL_x280-hotp-maximized.config | 94 + .../EOL_x280-maximized.config | 100 + config/coreboot-x280-maximized.config | 878 ++++ .../coreboot-x280-maximized.config_defconfig | 15 + config/linux-x280.config | 3764 +++++++++++++++++ modules/coreboot | 4 + .../0001-cbmem-include-endian.patch | 9 + ...klkbl_spd-Fix_integer_overflow_91170.patch | 38 + targets/x280_me_blobs.mk | 21 + 16 files changed, 5167 insertions(+), 62 deletions(-) delete mode 100644 blobs/xx80/README.md create mode 100755 blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh create mode 100644 blobs/xx80/x280_gbe.bin create mode 100644 blobs/xx80/x280_ifd.bin create mode 100644 boards/EOL_x280-hotp-maximized/EOL_x280-hotp-maximized.config create mode 100644 boards/EOL_x280-maximized/EOL_x280-maximized.config create mode 100644 config/coreboot-x280-maximized.config create mode 100644 config/coreboot-x280-maximized.config_defconfig create mode 100644 config/linux-x280.config create mode 100644 patches/coreboot-25.12/0001-cbmem-include-endian.patch create mode 100644 patches/coreboot-25.12/0002-mb_lenovo_sklkbl_spd-Fix_integer_overflow_91170.patch create mode 100644 targets/x280_me_blobs.mk diff --git a/.circleci/config.yml b/.circleci/config.yml index 191855454..c92ff7e66 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -167,6 +167,7 @@ jobs: command: | ./blobs/xx80/t480_download_clean_deguard_me_pad_tb.sh -m $(readlink -f ./blobs/utils/me_cleaner/me_cleaner.py) ./blobs/xx80/ ./blobs/xx80/t480s_download_clean_deguard_me_pad_tb.sh -m $(readlink -f ./blobs/utils/me_cleaner/me_cleaner.py) ./blobs/xx80/ + ./blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh -m $(readlink -f ./blobs/utils/me_cleaner/me_cleaner.py) ./blobs/xx80/ - run: name: Download, neuter and deguard m900 ME (keep generated GBE and extracted IFD in tree) command: | @@ -305,7 +306,7 @@ jobs: key: x86-coreboot-musl-cross-make-nix-docker-heads-{{ checksum "./tmpDir/coreboot_musl-cross-make.sha256sums" }}{{ .Environment.CACHE_VERSION }}-<< parameters.coreboot_dir >> paths: - build/x86/<< parameters.coreboot_dir >> - - build/x86/musl-cross-make-227df8b99103f9c59f6570babf892978e293082f + - build/x86/musl-cross-make-fd6be58297ee21fcba89216ccd0d4aca1e3f1c5c - crossgcc/x86 - install/x86 - packages/x86 @@ -406,7 +407,7 @@ jobs: key: ppc64-coreboot-musl-cross-make-nix-docker-heads-{{ checksum "./tmpDir/coreboot_musl-cross-make.sha256sums" }}{{ .Environment.CACHE_VERSION }}-<< parameters.coreboot_dir >> paths: - build/ppc64/<< parameters.coreboot_dir >> - - build/ppc64/musl-cross-make-227df8b99103f9c59f6570babf892978e293082f + - build/ppc64/musl-cross-make-fd6be58297ee21fcba89216ccd0d4aca1e3f1c5c - crossgcc/ppc64 - install/ppc64 - packages/ppc64 @@ -476,6 +477,15 @@ workflows: requires: - x86-musl-cross-make [cross compiler] + # 25.12 fork — builds coreboot-25.12 toolchain + - x86_coreboot: + name: EOL_x280-hotp-maximized [seed:coreboot-25.12] + target: EOL_x280-hotp-maximized + subcommand: "" + coreboot_dir: coreboot-25.12 + requires: + - x86-musl-cross-make [cross compiler] + # ── Dasharo shared toolchain ────────────────────────────────────────── # 4 forks share crossgcc (verified by sum-file diff). # novacustom-nv4x_adl is the only seed; all other Dasharo boards are @@ -527,6 +537,22 @@ workflows: requires: - x86-musl-cross-make [cross compiler] + # ── coreboot 25.12 boards X280 acts as seed ─────────────────────────────── + + - build: + name: EOL_x280-hotp-maximized + target: EOL_x280-hotp-maximized + subcommand: "" + requires: + - EOL_x280-hotp-maximized [seed:coreboot-25.12] + + - build: + name: EOL_x280-maximized + target: EOL_x280-maximized + subcommand: "" + requires: + - EOL_x280-hotp-maximized [seed:coreboot-25.12] + # ── coreboot 25.09 boards (alphabetical) ─────────────────────────────── - build: name: EOL_m900_tower-hotp-maximized diff --git a/.gitignore b/.gitignore index 766b9aced..352d0827f 100644 --- a/.gitignore +++ b/.gitignore @@ -26,3 +26,8 @@ typescript* result .claude/ tmpDir/ + +# Should have added this earlier +blobs/**/*.rom +blobs/**/*.fd +build/ diff --git a/blobs/xx80/README.md b/blobs/xx80/README.md deleted file mode 100644 index 87fbac58b..000000000 --- a/blobs/xx80/README.md +++ /dev/null @@ -1,60 +0,0 @@ -# T480 Blobs - -The following blobs are needed: - -* `ifd.bin` -* `gbe.bin` -* `me.bin` -* `tb.bin` (optional but recommended flashing this blob to the separate Thunderbolt SPI chip to fix a bug in the original firmware) - -## me.bin: automatically extract, deactivate, partially neuter and deguard - -download_clean_deguard_me_pad_tb.sh : Download vulnerable ME from Dell, verify checksum, extract ME, deactivate ME and paritally neuter it, then apply the deguard patch and place it into me.bin. -For the technical details please read the documentation in the script itself, as removing modules is limited on the platform. - -The ME blob dumped in this directory comes from the following link: https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe - -This provides ME version 11.6.0.1126. In this version CVE-2017-5705 has not yet been fixed. -See https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00086.html -Therefore, Bootguard can be disabled by deguard with a patched ME. - -As specified in the first link, this ME can be deployed to: - -* T480 -* T480s - -## ifd.bin and gbe.bin - -Both blobs were taken from libreboot: https://codeberg.org/libreboot/lbmk/src/commit/68ebde2f033ce662813dbf8f5ab21f160014029f/config/ifd/t480 - -The GBE MAC address was forged to: `00:DE:AD:C0:FF:EE MAC` - -## tb.bin - -This blob was extracted from https://download.lenovo.com/pccbbs/mobiles/n24th13w.exe -It is zero-padded to 1MB and should be flashed to the Thunderbolt SPI chip, which is not the same as the 16MB chip to which the heads rom is flashed. External flashing is recommended as the only way to reliably fix a bug in the original Thunderbolt software on the SPI chip. You can find a guide here: https://osresearch.net/T480-maximized-flashing/ - -## Integrity - -Sha256sums: `blobs/xx80/hashes.txt` - -# CAVEATS for the board: - -See the board configs `boards/t480-[hotp-]maximized/t480-[hotp-]maximized.config`: - -> This board is vulnerable to a TPM GPIO reset attack, i.e. the PCRs are reset while the system is running. -> This attack can be used to bypass measured boot when an attacker succeeds at modifying the SPI flash. -> Also it can be used to extract FDE keys from a TPM. -> The related coreboot issue contains more information: https://ticket.coreboot.org/issues/576 -> Make sure you understand the implications of the attack for your threat model before using this board. - -# Documentation - -A guide on how to flash this board (both the Heads rom and the Thunderbolt `tb.bin` blob) can be found here: -https://osresearch.net/T480-maximized-flashing/ - -The upstream documentation is available here. It includes a list of known issues: https://doc.coreboot.org/mainboard/lenovo/t480.html -Please note that some of the listed issues have been fixed under heads by using patches that are not yet merged upstream: -* headphone jack works as expected and is automatically detected when plugged in -* thunderbolt works -* lower USB-C port works diff --git a/blobs/xx80/hashes.txt b/blobs/xx80/hashes.txt index e3b6df2fd..16f17eb4f 100644 --- a/blobs/xx80/hashes.txt +++ b/blobs/xx80/hashes.txt @@ -8,3 +8,8 @@ f2f6d5fb0a5e02964b494862032fd93f1f88e2febd9904b936083600645c7fdf t480_ifd.bin b53e4670327e076ef879b2abef0efd9aade20da88d0c0976921b9f32378c0119 t480s_tb.bin caf6393cd5c4ff305b677f50c258658710c42439080868c1fb8ea7584cffb204 t480s_ifd.bin 36be39ecd0d06fa3f7893ca2746f702271c46b75de52bc599467a058bab8e271 t480s_gbe.bin +#X280: +fc67c1cafd11666a2f2702232e887ca413ce146ee25ec246ca94e60ac3083313 x280_tb.bin +404e08c7c9a4fd43c3b4da82012340ae360b3fbe299f4cb6b75344054d5fc936 x280_me.bin +4f0d11e9d62fe4d22fe2108ff35764f1bf2ad9131965e85f3cd43d6a1e83bb63 x280_ifd.bin +67ca8a1e91d31bb992bf8fddc1636b1df682bbb285b2c0701cfb4565924b8103 x280_gbe.bin diff --git a/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh b/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh new file mode 100755 index 000000000..16e9314c1 --- /dev/null +++ b/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh @@ -0,0 +1,206 @@ +#!/usr/bin/env bash + +# These variables are all for the deguard tool. +# They would need to be changed if using the tool for other devices like the X280 or with a different ME version... +ME_delta="thinkpad_x280" +ME_version="11.6.0.1126" +ME_sku="2M" +ME_pch="LP" + +# Thunderbolt firmware offset in bytes to pad to 1M +TBFW_SIZE=1048575 + +# Integrity checks for the vendor provided ME blob... +ME_DOWNLOAD_HASH="ddfbc51430699e0dfcb24a60bcb5b6e5481b325ebecf1ac177e069013189e4b0" +# ...and the cleaned and deguarded version from that blob. +# DEGUARDED_ME_BIN_HASH="404e08c7c9a4fd43c3b4da82012340ae360b3fbe299f4cb6b75344054d5fc936" +DEGUARDED_ME_BIN_HASH="6f1221c936a1bed60c057883d231d48ef23c4fa9" +# Integrity checks for the vendor provided Thunderbolt blob... +# still not sure it'll work +TB_DOWNLOAD_HASH="dcefadd999684d13a7909ee0bac17964209a6c4e6ebf5609ba72f9dab5e1d5b5" +# ...and the padded and flashable version from that blob. +# still not sure it'll work +TB_BIN_HASH="fc67c1cafd11666a2f2702232e887ca413ce146ee25ec246ca94e60ac3083313" + +function usage() { + echo -n \ + "Usage: $(basename "$0") -m (optional) path_to_output_directory +Download Intel ME firmware from Dell, neutralize and shrink keeping the MFS. +Download Thunderbolt firmware from Lenovo and pad it for flashing externally. +" +} + +function chk_sha256sum() { + sha256_hash="$1" + filename="$2" + echo "$sha256_hash" "$filename" "$(pwd)" + sha256sum "$filename" + if ! echo "${sha256_hash} ${filename}" | sha256sum --check; then + echo "ERROR: SHA256 checksum for ${filename} doesn't match." + + fi +} + +function chk_exists_and_matches() { + if [[ -f "$1" ]]; then + if echo "${2} ${1}" | sha256sum --check; then + echo "SKIPPING: SHA256 checksum for $1 matches." + [[ "$3" = ME ]] && me_exists="y" + [[ "$3" = TB ]] && tb_exists="y" + fi + echo "$1 exists but checksum doesn't match. Continuing..." + fi +} + +function download_and_clean() { + me_cleaner="$(realpath "${1}")" + me_output="$(realpath "${2}")" + + # Download and unpack the Dell installer into a temporary directory and + # extract the deguardable Intel ME blob. + pushd "$(mktemp -d)" || exit + + # Download the installer that contains the ME blob + me_installer_filename="Inspiron_5468_1.3.0.exe" + user_agent="Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Firefox/91.0" + curl -A "$user_agent" -s -O "https://dl.dell.com/FOLDER04573471M/1/${me_installer_filename}" + chk_sha256sum "$ME_DOWNLOAD_HASH" "$me_installer_filename" + + # Download the tool to unpack Dell's installer and unpack the ME blob. + git clone https://github.com/platomav/BIOSUtilities + git -C BIOSUtilities checkout ef50b75ae115ae8162fa8b0a7b8c42b1d2db894b + + python "BIOSUtilities/Dell_PFS_Extract.py" "${me_installer_filename}" -e || exit + + extracted_me_filename="1 Inspiron_5468_1.3.0 -- 3 Intel Management Engine (Non-VPro) Update v${ME_version}.bin" + + # Deactivate, partially neuter and shrink Intel ME. Note that this doesn't include + # --soft-disable to set the "ME Disable" or "ME Disable B" (e.g., + # High Assurance Program) bits, as they are defined within the Flash + # Descriptor. + # However, the HAP bit must be enabled to make the deguarded ME work. We only clean the ME in this function. + # For ME 11.x this means we must keep the rbe, bup, kernel and syslib modules. + # https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F#me-versions-from-11x-skylake-1 + # Furthermore, deguard requires keeping the MFS, the HAP bit set, and we cannot relocate the FTPR partition. + # Some more general info on shrinking: + # https://github.com/corna/me_cleaner/wiki/External-flashing#neutralize-and-shrink-intel-me-useful-only-for-coreboot + + # MFS is needed for deguard so we whitelist it here and also do not relocate the FTPR partition + python "$me_cleaner" --whitelist MFS -t -O "$me_output" "${me_installer_filename}_extracted/Firmware/${extracted_me_filename}" + rm -rf ./* + popd || exit +} + +function deguard() { + me_input="$(realpath "${1}")" + me_output="$(realpath "${2}")" + + # Download the deguard tool into a temporary directory and apply the patch to the cleaned ME blob. + pushd "$(mktemp -d)" || exit + git clone https://github.com/coreboot/deguard + pushd deguard || exit + git checkout 4944584c7cc0201adcc89a0465ab60f7f9f50ac6 + + python ./finalimage.py \ + --delta "data/delta/$ME_delta" \ + --version "$ME_version" \ + --pch "$ME_pch" \ + --sku "$ME_sku" \ + --fake-fpfs data/fpfs/zero \ + --input "$me_input" \ + --output "$me_output" + + popd || exit + #Cleanup + rm -rf ./* + popd || exit +} + +function download_and_pad_tb() { + tb_output="$(realpath "${1}")" + + # Download and unpack the Lenovo installer into a temporary directory and + # extract the TB blob. + pushd "$(mktemp -d)" || exit + + # Download the installer that contains the TB blob + tb_installer_filename=""n20th12w.exe"" + user_agent="Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Firefox/91.0" + curl -A "$user_agent" -s -O "https://download.lenovo.com/pccbbs/mobiles/${tb_installer_filename}" + chk_sha256sum "$TB_DOWNLOAD_HASH" "$tb_installer_filename" + + # https://www.reddit.com/r/thinkpad/comments/9rnimi/ladies_and_gentlemen_i_present_to_you_the/ + innoextract n20th12w.exe -d . + mv ./code\$GetExtractPath\$/TBT.bin tb.bin + # pad with zeros + dd if=/dev/zero of=tb.bin bs=1 seek="$TBFW_SIZE" count=1 + mv "tb.bin" "$tb_output" + + rm -rf ./* + popd || exit +} + +function usage_err() { + echo "$1" + usage + exit 1 +} + +function parse_params() { + while getopts ":m:" opt; do + case $opt in + m) + if [[ -x "$OPTARG" ]]; then + me_cleaner="$OPTARG" + fi + ;; + ?) + usage_err "Invalid Option: -$OPTARG" + ;; + esac + done + + if [[ -z "${me_cleaner}" ]]; then + if [[ -z "${COREBOOT_DIR}" ]]; then + usage_err "ERROR: me_cleaner.py not found. Set path with -m parameter or define the COREBOOT_DIR variable." + else + me_cleaner="${COREBOOT_DIR}/util/me_cleaner/me_cleaner.py" + fi + fi + echo "Using me_cleaner from ${me_cleaner}" + + shift $(($OPTIND - 1)) + output_dir="$(realpath "${1:-./}")" + if [[ ! -d "${output_dir}" ]]; then + usage_err "No valid output dir found" + fi + me_cleaned="${output_dir}/me_cleaned.bin" + me_deguarded="${output_dir}/x280_me.bin" + tb_flashable="${output_dir}/x280_tb.bin" + echo "Writing cleaned and deguarded ME to ${me_deguarded}" + echo "Writing flashable TB to ${tb_flashable}" +} + +if [[ "${BASH_SOURCE[0]}" == "$0" ]]; then + if [[ "${1:-}" == "--help" ]]; then + usage + exit 0 + fi + + parse_params "$@" + chk_exists_and_matches "$me_deguarded" "$DEGUARDED_ME_BIN_HASH" ME + chk_exists_and_matches "$tb_flashable" "$TB_BIN_HASH" TB + + if [[ -z "$me_exists" ]]; then + download_and_clean "$me_cleaner" "$me_cleaned" + deguard "$me_cleaned" "$me_deguarded" + rm -f "$me_cleaned" + fi + + if [[ -z "$tb_exists" ]]; then + download_and_pad_tb "$tb_flashable" + fi + + chk_sha256sum "$DEGUARDED_ME_BIN_HASH" "$me_deguarded" + chk_sha256sum "$TB_BIN_HASH" "$tb_flashable" +fi diff --git a/blobs/xx80/x280_gbe.bin b/blobs/xx80/x280_gbe.bin new file mode 100644 index 0000000000000000000000000000000000000000..0124ba42d7cd342033f62c92115df28624482392 GIT binary patch literal 8192 zcmbR7Yqr4Gos1m+|BEo3XJBYx5cvQ9ut1p7D)H;03^35Z%AjMwAO_^}Bxx~mIdcdz zUKd@v>$>O-FbQG-wKg#LwQ+#7urn|yD1aDzK+MSCpdrNW@E-#(F#Z2Oj~Ap26Ce~% z*}%ZT#lSLQgS&&up@WLQ8xrIh7(4_R9Dp>-ML`B;E+L?HAbX1egA9Wq0~?U$1k&t4 zS^!9M0ci;!%>$)*p)})P0|uQrh73O23>a8}@(3G8S)(B^azY?8xP_S!GXsu_poIXl zEt&w3yN3r;Y*b`41V{~mkyF}?`gAk|MnhmU1V%$(Gz3ON02Bg#Mg~Ey2BzUYzJC7k zK8}9$4i$!bYY+T?N3j3DoHqS`DOc=mB}6EU_Wu!KG0GYZ0cwZ9X#XF334|^>+W$un lkx@RiLV((Ndepqp5Eu=C(GVC7fzc2c4S~TO0t4Ou2LPVHS;7DS literal 0 HcmV?d00001 diff --git a/blobs/xx80/x280_ifd.bin b/blobs/xx80/x280_ifd.bin new file mode 100644 index 0000000000000000000000000000000000000000..b9c7f858e5946549201d3233af9b23f01de9c358 GIT binary patch literal 4096 zcmeHKu}T9$6r8=yVG_igB*g_HuEn(y^#crn!zPWzHKL&42c)$!mA#c;U}-H{ir{DX z38skH9IW&14#^o!l|teU%v*Ne+xK?osuINsgrpWfX+ zJikZ|L`zwoX(|N|_7Xqyd!u461HLHDik`oeFI)x=0VRW{L19MI)NTglL|!zcs6F7k zXwlvVod8xzL-xoG67aLQ#waHT6csh86`VxC^|)?7(lpJ4Y8HV`u}VYYfb5d{I>3l) zljQWg&E%}s=I$a%l1&cLE2=I7YG^Rp>;~~wb^t~$LQM85Gv9gPM*q=<2>7i=>j=ah z2j_ruz&YR?a1J;JoCD4Q=fILV@MJ>7CN^)q5Rr+Dc?{tj-*krgx@6Ct` + /* SPDX-License-Identifier: GPL-2.0-only */ + + #include diff --git a/patches/coreboot-25.12/0002-mb_lenovo_sklkbl_spd-Fix_integer_overflow_91170.patch b/patches/coreboot-25.12/0002-mb_lenovo_sklkbl_spd-Fix_integer_overflow_91170.patch new file mode 100644 index 000000000..b7198911a --- /dev/null +++ b/patches/coreboot-25.12/0002-mb_lenovo_sklkbl_spd-Fix_integer_overflow_91170.patch @@ -0,0 +1,38 @@ +From 3b9fae176d9ef65be7f3baeec1f4ffda3b5a1bbb Mon Sep 17 00:00:00 2001 +From: "Johann C. Rode" +Date: Wed, 11 Feb 2026 20:07:01 -0800 +Subject: [PATCH] mb/lenovo/sklkbl/spd: Fix integer overflow + +This fixes an integer overflow in the calculation of the offset within +the SPD binary that has caused memory detection failures on some +machines (e.g. this resolves https://ticket.coreboot.org/issues/627 ). +In a nutshell, spd_index (uint8_t) receives an assigned multiplication +by 512 (SPD_SIZE_MAX_DDR4) which will always truncate the result. + +Change-Id: I048a73c18c9a3d1b20e2a4276e1714e59550eaf5 +Signed-off-by: Johann C. Rode +Reviewed-on: https://review.coreboot.org/c/coreboot/+/91170 +Reviewed-by: Patrick Rudolph +Reviewed-by: Angel Pons +Tested-by: build bot (Jenkins) +--- + src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c +index 6ce18e5167..eaff251cc7 100644 +--- a/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c ++++ b/src/mainboard/lenovo/sklkbl_thinkpad/spd/spd.c +@@ -28,8 +28,7 @@ uint8_t *mainboard_find_spd_data(uint8_t spd_index) + die("Missing SPD data (spd.bin size %zu smaller than SPD size %u).", spd_file_len, SPD_SIZE_MAX_DDR4); + + /* Assume same memory in both channels */ +- spd_index *= SPD_SIZE_MAX_DDR4; +- spd_data = (uint8_t *)(spd_file + spd_index); ++ spd_data = (uint8_t *)(spd_file + spd_index * SPD_SIZE_MAX_DDR4); + + /* Make sure a valid SPD was found */ + if (spd_data[0] == 0) +-- +2.55.0 + diff --git a/targets/x280_me_blobs.mk b/targets/x280_me_blobs.mk new file mode 100644 index 000000000..589a4f58b --- /dev/null +++ b/targets/x280_me_blobs.mk @@ -0,0 +1,21 @@ +# Targets for downloading xx80 ME blob, neutering it and deactivating ME. +# This also uses the deguard tool to bypass Intel Boot Guard exploiting CVE-2017-5705. +# See https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00086.html + +# xx80-*-maximized boards require of you initially call one of the +# following to have gbe.bin ifd.bin and me.bin +# - blobs/xx80/download_clean_me_and_deguard.sh +# To download Lenovo original ME binary, neuter+deactivate ME, produce +# reduced IFD ME region and expanded BIOS IFD region. +# Also creates the tb.bin blob to flash the Thunderbolt SPI. + +# Make the Coreboot build depend on the following 3rd party blobs: +$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \ + $(pwd)/blobs/xx80/x280_me.bin $(pwd)/blobs/xx80/x280_tb.bin $(build)/$(BOARD)/x280_tb.bin + +$(pwd)/blobs/xx80/x280_me.bin $(pwd)/blobs/xx80/x280_tb.bin &: + $(pwd)/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh \ + -m $(pwd)/blobs/utils/me_cleaner/me_cleaner.py $(pwd)/blobs/xx80 + +$(build)/$(BOARD)/x280_tb.bin: $(pwd)/blobs/xx80/x280_tb.bin + cp $(pwd)/blobs/xx80/x280_tb.bin $(build)/$(BOARD) From 43c207c63f79b8ce4bb38293b5cbc79be0efce16 Mon Sep 17 00:00:00 2001 From: NobodyNo0ne Date: Thu, 27 Aug 2026 18:57:19 +0100 Subject: [PATCH 2/7] Patch applies cleanly with no changes. I thought I already did this. Same with fixing a couple lines in CircleCI. Added back blobs README, with minor edits to mention the X280 Signed-off-by: NobodyNo0ne --- .circleci/config.yml | 2 +- blobs/xx80/README.md | 61 +++ config/coreboot-x280-maximized.config | 1 + ...wn-Allow-locking-down-SPI-and-LPC-in.patch | 427 ++++++++++++++++++ 4 files changed, 490 insertions(+), 1 deletion(-) create mode 100644 blobs/xx80/README.md create mode 100644 patches/coreboot-25.12/0003-soc-intel-lockdown-Allow-locking-down-SPI-and-LPC-in.patch diff --git a/.circleci/config.yml b/.circleci/config.yml index c92ff7e66..760d2ed5e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -407,7 +407,7 @@ jobs: key: ppc64-coreboot-musl-cross-make-nix-docker-heads-{{ checksum "./tmpDir/coreboot_musl-cross-make.sha256sums" }}{{ .Environment.CACHE_VERSION }}-<< parameters.coreboot_dir >> paths: - build/ppc64/<< parameters.coreboot_dir >> - - build/ppc64/musl-cross-make-fd6be58297ee21fcba89216ccd0d4aca1e3f1c5c + - build/ppc64/musl-cross-make-227df8b99103f9c59f6570babf892978e293082f - crossgcc/ppc64 - install/ppc64 - packages/ppc64 diff --git a/blobs/xx80/README.md b/blobs/xx80/README.md new file mode 100644 index 000000000..76cb61be9 --- /dev/null +++ b/blobs/xx80/README.md @@ -0,0 +1,61 @@ +# xx80 Blobs + +The following blobs are needed: + +* `ifd.bin` +* `gbe.bin` +* `me.bin` +* `tb.bin` (optional but recommended flashing this blob to the separate Thunderbolt SPI chip to fix a bug in the original firmware) + +## me.bin: automatically extract, deactivate, partially neuter and deguard + +download_clean_deguard_me_pad_tb.sh : Download vulnerable ME from Dell, verify checksum, extract ME, deactivate ME and paritally neuter it, then apply the deguard patch and place it into me.bin. +For the technical details please read the documentation in the script itself, as removing modules is limited on the platform. + +The ME blob dumped in this directory comes from the following link: https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe + +This provides ME version 11.6.0.1126. In this version CVE-2017-5705 has not yet been fixed. +See https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00086.html +Therefore, Bootguard can be disabled by deguard with a patched ME. + +As specified in the first link, this ME can be deployed to: + +* T480 +* T480s +* X280 + +## ifd.bin and gbe.bin + +Both blobs were taken from libreboot: https://codeberg.org/libreboot/lbmk/src/commit/68ebde2f033ce662813dbf8f5ab21f160014029f/config/ifd/t480 + +The GBE MAC address was forged to: `00:DE:AD:C0:FF:EE MAC` + +## tb.bin + +This blob was extracted from https://download.lenovo.com/pccbbs/mobiles/n24th13w.exe +It is zero-padded to 1MB and should be flashed to the Thunderbolt SPI chip, which is not the same as the 16MB chip to which the heads rom is flashed. External flashing is recommended as the only way to reliably fix a bug in the original Thunderbolt software on the SPI chip. You can find a guide here: https://osresearch.net/T480-maximized-flashing/ + +## Integrity + +Sha256sums: `blobs/xx80/hashes.txt` + +# CAVEATS for the board: + +See the board configs `boards/t480-[hotp-]maximized/t480-[hotp-]maximized.config`: + +> This board is vulnerable to a TPM GPIO reset attack, i.e. the PCRs are reset while the system is running. +> This attack can be used to bypass measured boot when an attacker succeeds at modifying the SPI flash. +> Also it can be used to extract FDE keys from a TPM. +> The related coreboot issue contains more information: https://ticket.coreboot.org/issues/576 +> Make sure you understand the implications of the attack for your threat model before using this board. + +# Documentation + +A guide on how to flash this board (both the Heads rom and the Thunderbolt `tb.bin` blob) can be found here: +https://osresearch.net/T480-maximized-flashing/ + +The upstream documentation is available here. It includes a list of known issues: https://doc.coreboot.org/mainboard/lenovo/t480.html +Please note that some of the listed issues have been fixed under heads by using patches that are not yet merged upstream: +* headphone jack works as expected and is automatically detected when plugged in +* thunderbolt works +* lower USB-C port works diff --git a/config/coreboot-x280-maximized.config b/config/coreboot-x280-maximized.config index 3583806a2..a57cad922 100644 --- a/config/coreboot-x280-maximized.config +++ b/config/coreboot-x280-maximized.config @@ -719,6 +719,7 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y # CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set # CONFIG_BOOTMEDIA_LOCK_CHIP is not set # CONFIG_BOOTMEDIA_SMM_BWP is not set +CONFIG_BOOTMEDIA_SMM_BWP_RUNTIME_OPTION=y # end of Security CONFIG_ACPI_HAVE_PCAT_8259=y diff --git a/patches/coreboot-25.12/0003-soc-intel-lockdown-Allow-locking-down-SPI-and-LPC-in.patch b/patches/coreboot-25.12/0003-soc-intel-lockdown-Allow-locking-down-SPI-and-LPC-in.patch new file mode 100644 index 000000000..b5f7aa404 --- /dev/null +++ b/patches/coreboot-25.12/0003-soc-intel-lockdown-Allow-locking-down-SPI-and-LPC-in.patch @@ -0,0 +1,427 @@ +From d8ee9def7fe87b647cdeb951485efc679d119d86 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Sat, 23 Nov 2024 22:43:10 +0100 +Subject: [PATCH 3/5] soc/intel/lockdown: Allow locking down SPI and LPC in SMM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Heads payload uses APM_CNT_FINALIZE SMI to set and lock down the SPI +controller with PR0 flash protection for pre-Skylake platforms. + +Add new option to skip LPC and FAST SPI lock down in coreboot and move +it to APM_CNT_FINALIZE SMI handler. Reuse the INTEL_CHIPSET_LOCKDOWN +option to prevent issuing APM_CNT_FINALIZE SMI on normal boot path, +like it was done on pre-Skylake platforms. As the locking on modern +SOCs became more complicated, separate the SPI and LPC locking into +new modules to make linking to SMM easier. + +The expected configuration to leverage the feautre is to unselect +INTEL_CHIPSET_LOCKDOWN and select SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM. + +Testing various microarchitectures happens on heads repository: +https://github.com/linuxboot/heads/pull/1818 + +TEST=Lock the SPI flash using APM_CNT_FINALIZE in heads on Alder Lake +(Protectli VP66xx) and Comet Lake (Protectli VP46xx) platforms. Check +if flash is unlocked in the heads recovery console. Check if flash is +locked in the kexec'ed OS. + +Change-Id: Icbcc6fcde90e5b0a999aacb720e2e3dc2748c838 +Signed-off-by: Michał Żygowski +--- + src/soc/intel/alderlake/finalize.c | 4 +- + src/soc/intel/cannonlake/finalize.c | 4 +- + src/soc/intel/common/block/lpc/Makefile.mk | 4 ++ + src/soc/intel/common/block/smm/smihandler.c | 10 ++++ + .../common/pch/include/intelpch/lockdown.h | 3 ++ + src/soc/intel/common/pch/lockdown/Kconfig | 15 ++++++ + src/soc/intel/common/pch/lockdown/Makefile.mk | 5 ++ + src/soc/intel/common/pch/lockdown/lockdown.c | 48 ++----------------- + .../intel/common/pch/lockdown/lockdown_lpc.c | 23 +++++++++ + .../intel/common/pch/lockdown/lockdown_spi.c | 32 +++++++++++++ + src/soc/intel/denverton_ns/lpc.c | 3 +- + src/soc/intel/elkhartlake/finalize.c | 4 +- + src/soc/intel/jasperlake/finalize.c | 3 +- + src/soc/intel/meteorlake/finalize.c | 4 +- + src/soc/intel/pantherlake/finalize.c | 4 +- + src/soc/intel/skylake/finalize.c | 3 +- + src/soc/intel/tigerlake/finalize.c | 4 +- + 17 files changed, 121 insertions(+), 52 deletions(-) + create mode 100644 src/soc/intel/common/pch/lockdown/lockdown_lpc.c + create mode 100644 src/soc/intel/common/pch/lockdown/lockdown_spi.c + +diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c +index 700fde977b..615729d3dd 100644 +--- a/src/soc/intel/alderlake/finalize.c ++++ b/src/soc/intel/alderlake/finalize.c +@@ -85,7 +85,9 @@ static void soc_finalize(void *unused) + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); ++ + tbt_finalize(); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && + CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) +diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c +index 974794bd97..461ba3a884 100644 +--- a/src/soc/intel/cannonlake/finalize.c ++++ b/src/soc/intel/cannonlake/finalize.c +@@ -87,7 +87,9 @@ static void soc_finalize(void *unused) + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); ++ + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && + CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) + heci1_disable(); +diff --git a/src/soc/intel/common/block/lpc/Makefile.mk b/src/soc/intel/common/block/lpc/Makefile.mk +index b510cd0ec3..60792654b5 100644 +--- a/src/soc/intel/common/block/lpc/Makefile.mk ++++ b/src/soc/intel/common/block/lpc/Makefile.mk +@@ -5,3 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c + + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c ++ ++ifeq ($(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM),y) ++smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ++endif +diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c +index 59489a4f03..2a1f26d2eb 100644 +--- a/src/soc/intel/common/block/smm/smihandler.c ++++ b/src/soc/intel/common/block/smm/smihandler.c +@@ -14,12 +14,14 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + #include + #include + #include +@@ -345,6 +347,14 @@ static void finalize(void) + } + finalize_done = 1; + ++ if (CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) { ++ /* SPI lock down configuration */ ++ fast_spi_lockdown_bios(CHIPSET_LOCKDOWN_COREBOOT); ++ ++ /* LPC/eSPI lock down configuration */ ++ lpc_lockdown_config(CHIPSET_LOCKDOWN_COREBOOT); ++ } ++ + if (CONFIG(SPI_FLASH_SMM)) + /* Re-init SPI driver to handle locked BAR */ + fast_spi_init(); +diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h +index b5aba06fe0..1b96f41a2a 100644 +--- a/src/soc/intel/common/pch/include/intelpch/lockdown.h ++++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h +@@ -22,4 +22,7 @@ int get_lockdown_config(void); + */ + void soc_lockdown_config(int chipset_lockdown); + ++void fast_spi_lockdown_bios(int chipset_lockdown); ++void lpc_lockdown_config(int chipset_lockdown); ++ + #endif /* SOC_INTEL_COMMON_PCH_LOCKDOWN_H */ +diff --git a/src/soc/intel/common/pch/lockdown/Kconfig b/src/soc/intel/common/pch/lockdown/Kconfig +index 38f60d2056..545185c52f 100644 +--- a/src/soc/intel/common/pch/lockdown/Kconfig ++++ b/src/soc/intel/common/pch/lockdown/Kconfig +@@ -3,7 +3,22 @@ + config SOC_INTEL_COMMON_PCH_LOCKDOWN + bool + default n ++ select HAVE_INTEL_CHIPSET_LOCKDOWN + help + This option allows to have chipset lockdown for DMI, FAST_SPI and + soc_lockdown_config() to implement any additional lockdown as PMC, + LPC for supported PCH. ++ ++config SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM ++ bool "Lock down SPI controller in SMM" ++ default n ++ depends on HAVE_SMI_HANDLER && !INTEL_CHIPSET_LOCKDOWN ++ select SPI_FLASH_SMM ++ help ++ This option allows to have chipset lockdown for FAST_SPI and LPC for ++ supported PCH. If selected, coreboot will skip locking down the SPI ++ and LPC controller. The payload or OS is responsible for locking it ++ using APM_CNT_FINALIZE SMI. Used by heads to set and lock PR0 flash ++ protection. ++ ++ If unsure, say N. +diff --git a/src/soc/intel/common/pch/lockdown/Makefile.mk b/src/soc/intel/common/pch/lockdown/Makefile.mk +index 71466f8edd..64aad562ac 100644 +--- a/src/soc/intel/common/pch/lockdown/Makefile.mk ++++ b/src/soc/intel/common/pch/lockdown/Makefile.mk +@@ -1,2 +1,7 @@ + ## SPDX-License-Identifier: GPL-2.0-only + ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown.c ++ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_lpc.c ++ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_spi.c ++ ++smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_lpc.c ++smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_spi.c +diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c +index eec3beb01b..2d229e1a90 100644 +--- a/src/soc/intel/common/pch/lockdown/lockdown.c ++++ b/src/soc/intel/common/pch/lockdown/lockdown.c +@@ -60,56 +60,17 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown) + /* Set FAST_SPI opcode menu */ + fast_spi_set_opcode_menu(); + +- /* Discrete Lock Flash PR registers */ +- fast_spi_pr_dlock(); +- + /* Check if SPI transaction is pending */ + fast_spi_cycle_in_progress(); + + /* Clear any outstanding status bits like AEL, FCERR, FDONE, SAF etc. */ + fast_spi_clear_outstanding_status(); + +- /* Lock FAST_SPIBAR */ +- fast_spi_lock_bar(); +- + /* Set Vendor Component Lock (VCL) */ + fast_spi_vscc0_lock(); + +- /* Set BIOS Interface Lock, BIOS Lock */ +- if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { +- /* BIOS Interface Lock */ +- fast_spi_set_bios_interface_lock_down(); +- +- /* Only allow writes in SMM */ +- if (CONFIG(BOOTMEDIA_SMM_BWP)) { +- fast_spi_set_eiss(); +- fast_spi_enable_wp(); +- } +- +- /* BIOS Lock */ +- fast_spi_set_lock_enable(); +- +- /* EXT BIOS Lock */ +- fast_spi_set_ext_bios_lock_enable(); +- } +-} +- +-static void lpc_lockdown_config(int chipset_lockdown) +-{ +- /* Set BIOS Interface Lock, BIOS Lock */ +- if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { +- /* BIOS Interface Lock */ +- lpc_set_bios_interface_lock_down(); +- +- /* Only allow writes in SMM */ +- if (CONFIG(BOOTMEDIA_SMM_BWP)) { +- lpc_set_eiss(); +- lpc_enable_wp(); +- } +- +- /* BIOS Lock */ +- lpc_set_lock_enable(); +- } ++ if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) ++ fast_spi_lockdown_bios(chipset_lockdown); + } + + static void sa_lockdown_config(int chipset_lockdown) +@@ -135,8 +96,9 @@ static void platform_lockdown_config(void *unused) + /* SPI lock down configuration */ + fast_spi_lockdown_cfg(chipset_lockdown); + +- /* LPC/eSPI lock down configuration */ +- lpc_lockdown_config(chipset_lockdown); ++ if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) ++ /* LPC/eSPI lock down configuration */ ++ lpc_lockdown_config(chipset_lockdown); + + /* GPMR lock down configuration */ + gpmr_lockdown_cfg(); +diff --git a/src/soc/intel/common/pch/lockdown/lockdown_lpc.c b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c +new file mode 100644 +index 0000000000..69278ea343 +--- /dev/null ++++ b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c +@@ -0,0 +1,23 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++ ++void lpc_lockdown_config(int chipset_lockdown) ++{ ++ /* Set BIOS Interface Lock, BIOS Lock */ ++ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { ++ /* BIOS Interface Lock */ ++ lpc_set_bios_interface_lock_down(); ++ ++ /* Only allow writes in SMM */ ++ if (CONFIG(BOOTMEDIA_SMM_BWP)) { ++ lpc_set_eiss(); ++ lpc_enable_wp(); ++ } ++ ++ /* BIOS Lock */ ++ lpc_set_lock_enable(); ++ } ++} +diff --git a/src/soc/intel/common/pch/lockdown/lockdown_spi.c b/src/soc/intel/common/pch/lockdown/lockdown_spi.c +new file mode 100644 +index 0000000000..8dbe93013e +--- /dev/null ++++ b/src/soc/intel/common/pch/lockdown/lockdown_spi.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++ ++void fast_spi_lockdown_bios(int chipset_lockdown) ++{ ++ /* Discrete Lock Flash PR registers */ ++ fast_spi_pr_dlock(); ++ ++ /* Lock FAST_SPIBAR */ ++ fast_spi_lock_bar(); ++ ++ /* Set BIOS Interface Lock, BIOS Lock */ ++ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { ++ /* BIOS Interface Lock */ ++ fast_spi_set_bios_interface_lock_down(); ++ ++ /* Only allow writes in SMM */ ++ if (CONFIG(BOOTMEDIA_SMM_BWP)) { ++ fast_spi_set_eiss(); ++ fast_spi_enable_wp(); ++ } ++ ++ /* BIOS Lock */ ++ fast_spi_set_lock_enable(); ++ ++ /* EXT BIOS Lock */ ++ fast_spi_set_ext_bios_lock_enable(); ++ } ++} +diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c +index 7dc971ea92..c4f7681c62 100644 +--- a/src/soc/intel/denverton_ns/lpc.c ++++ b/src/soc/intel/denverton_ns/lpc.c +@@ -536,7 +536,8 @@ static const struct pci_driver lpc_driver __pci_driver = { + + static void finalize_chipset(void *unused) + { +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); + } + + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c +index 275413b4ef..fc54710303 100644 +--- a/src/soc/intel/elkhartlake/finalize.c ++++ b/src/soc/intel/elkhartlake/finalize.c +@@ -43,7 +43,9 @@ static void soc_finalize(void *unused) + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); ++ + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && + CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + heci_finalize(); +diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c +index 8788db155d..4840c0c04c 100644 +--- a/src/soc/intel/jasperlake/finalize.c ++++ b/src/soc/intel/jasperlake/finalize.c +@@ -76,7 +76,8 @@ static void soc_finalize(void *unused) + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); + + /* Indicate finalize step with post code */ + post_code(POSTCODE_OS_BOOT); +diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c +index 1fd1d98fb5..80802db285 100644 +--- a/src/soc/intel/meteorlake/finalize.c ++++ b/src/soc/intel/meteorlake/finalize.c +@@ -64,7 +64,9 @@ static void soc_finalize(void *unused) + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); ++ + tbt_finalize(); + sa_finalize(); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && +diff --git a/src/soc/intel/pantherlake/finalize.c b/src/soc/intel/pantherlake/finalize.c +index 05ec3eaaca..1d47dd7a0b 100644 +--- a/src/soc/intel/pantherlake/finalize.c ++++ b/src/soc/intel/pantherlake/finalize.c +@@ -63,7 +63,9 @@ static void soc_finalize(void *unused) + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); ++ + tbt_finalize(); + sa_finalize(); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && +diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c +index fd80aeac1a..a147b62e46 100644 +--- a/src/soc/intel/skylake/finalize.c ++++ b/src/soc/intel/skylake/finalize.c +@@ -106,7 +106,8 @@ static void soc_finalize(void *unused) + pch_finalize_script(dev); + + soc_lockdown(dev); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); + + /* Indicate finalize step with post code */ + post_code(POSTCODE_OS_BOOT); +diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c +index cd02745a9e..158b2fb691 100644 +--- a/src/soc/intel/tigerlake/finalize.c ++++ b/src/soc/intel/tigerlake/finalize.c +@@ -55,7 +55,9 @@ static void soc_finalize(void *unused) + printk(BIOS_DEBUG, "Finalizing chipset.\n"); + + pch_finalize(); +- apm_control(APM_CNT_FINALIZE); ++ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) ++ apm_control(APM_CNT_FINALIZE); ++ + tbt_finalize(); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + heci1_disable(); +-- +2.39.5 + From db8d86786b0f126f4886ca68ca091d58b57ccdf9 Mon Sep 17 00:00:00 2001 From: Thierry Laurion Date: Thu, 27 Aug 2026 15:16:34 -0400 Subject: [PATCH 3/7] gitignore: ignore *.bin, drop stale blobs/build entries Signed-off-by: Thierry Laurion --- .gitignore | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 352d0827f..b6b236a25 100644 --- a/.gitignore +++ b/.gitignore @@ -19,6 +19,7 @@ *~ .*.sw* /.direnv +*.bin clean config/*.old crossgcc @@ -26,8 +27,3 @@ typescript* result .claude/ tmpDir/ - -# Should have added this earlier -blobs/**/*.rom -blobs/**/*.fd -build/ From dc715ead5ab28a9ee5ca23a9d658505b8212b612 Mon Sep 17 00:00:00 2001 From: Thierry Laurion Date: Thu, 27 Aug 2026 15:16:42 -0400 Subject: [PATCH 4/7] circleci: fix musl-cross-make cache key hash for x280 port Signed-off-by: Thierry Laurion --- .circleci/config.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 760d2ed5e..e35cea0aa 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -306,7 +306,7 @@ jobs: key: x86-coreboot-musl-cross-make-nix-docker-heads-{{ checksum "./tmpDir/coreboot_musl-cross-make.sha256sums" }}{{ .Environment.CACHE_VERSION }}-<< parameters.coreboot_dir >> paths: - build/x86/<< parameters.coreboot_dir >> - - build/x86/musl-cross-make-fd6be58297ee21fcba89216ccd0d4aca1e3f1c5c + - build/x86/musl-cross-make-227df8b99103f9c59f6570babf892978e293082f - crossgcc/x86 - install/x86 - packages/x86 From 0b678c5529d38010108780805baa92a21366ad7b Mon Sep 17 00:00:00 2001 From: Thierry Laurion Date: Thu, 27 Aug 2026 15:16:50 -0400 Subject: [PATCH 5/7] x280 coreboot config: t480-derived config, regenerate with helpers Standardize the x280-maximized coreboot config against the t480 board and regenerate with the module helpers: make BOARD=x280-maximized coreboot.save_in_oldconfig_format_in_place make BOARD=x280-maximized coreboot.save_in_defconfig_format_backup Signed-off-by: Thierry Laurion --- config/coreboot-x280-maximized.config | 49 ++++++++++++++++++++------- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/config/coreboot-x280-maximized.config b/config/coreboot-x280-maximized.config index a57cad922..db9a60c7d 100644 --- a/config/coreboot-x280-maximized.config +++ b/config/coreboot-x280-maximized.config @@ -6,7 +6,7 @@ # # General setup # -CONFIG_LOCALVERSION="Heads-" +CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set @@ -34,7 +34,12 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_NO_STAGE_CACHE is not set CONFIG_TSEG_STAGE_CACHE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_BOOTSPLASH_IMAGE is not set +CONFIG_BOOTSPLASH_IMAGE=y +CONFIG_BOOTSPLASH_FILE="@BRAND_DIR@/bootsplash.jpg" +CONFIG_BOOTSPLASH_CONVERT=y +CONFIG_BOOTSPLASH_CONVERT_QUALITY=90 +# CONFIG_BOOTSPLASH_CONVERT_RESIZE is not set +# CONFIG_BOOTSPLASH_CONVERT_COLORSWAP is not set # # Software Bill Of Materials (SBOM) @@ -124,6 +129,8 @@ CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0xEEC000 # CONFIG_CONSOLE_SERIAL is not set +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_DUAL=y CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_QUAD=y CONFIG_MAX_CPUS=8 @@ -169,6 +176,9 @@ CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y # CONFIG_DEBUG_SMI is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -233,7 +243,7 @@ CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown" CONFIG_EC_STARLABS_BATTERY_TYPE="LION" CONFIG_EC_STARLABS_BATTERY_OEM="Unknown" # CONFIG_TPM_MEASURED_BOOT is not set -CONFIG_LINUX_COMMAND_LINE="console=tty0 loglevel=7" +CONFIG_LINUX_COMMAND_LINE="quiet loglevel=2" CONFIG_BOARD_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -253,10 +263,10 @@ CONFIG_COREBOOT_ROMSIZE_KB=16384 CONFIG_ROM_SIZE=0x01000000 CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y -# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set -CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set # CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set -CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 # end of Mainboard CONFIG_SYSTEM_TYPE_LAPTOP=y @@ -426,6 +436,7 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y CONFIG_SOC_INTEL_COMMON_PCH_BASE=y CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM=y CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y @@ -480,11 +491,13 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 CONFIG_RCBA_LENGTH=0x4000 @@ -572,8 +585,14 @@ CONFIG_NO_EARLY_GFX_INIT=y # # Display # -CONFIG_VGA_TEXT_FRAMEBUFFER=y -# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +CONFIG_BOOTSPLASH=y +CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y +# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set +# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set CONFIG_DEFAULT_SCREEN_ROTATION_INT=0 # end of Display @@ -589,6 +608,9 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x800 # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -616,6 +638,7 @@ CONFIG_MRC_SETTINGS_PROTECT=y CONFIG_SPI_FLASH=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +CONFIG_SPI_FLASH_SMM=y # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_TPM_INIT_RAMSTAGE=y # CONFIG_TPM_PPI is not set @@ -668,7 +691,6 @@ CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_MEMORY_MAPPED_TPM=y CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 -CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_USB_ACPI=y CONFIG_DRIVERS_WIFI_GENERIC=y @@ -715,11 +737,12 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y # CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set -CONFIG_BOOTMEDIA_LOCK_NONE=y -# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_NONE is not set +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y # CONFIG_BOOTMEDIA_LOCK_CHIP is not set +CONFIG_BOOTMEDIA_LOCK_WHOLE_RO=y +# CONFIG_BOOTMEDIA_LOCK_WHOLE_NO_ACCESS is not set # CONFIG_BOOTMEDIA_SMM_BWP is not set -CONFIG_BOOTMEDIA_SMM_BWP_RUNTIME_OPTION=y # end of Security CONFIG_ACPI_HAVE_PCAT_8259=y From 5209b7bf8e8abaf6a2885478c8213419d920c0c1 Mon Sep 17 00:00:00 2001 From: Thierry Laurion Date: Thu, 27 Aug 2026 15:16:59 -0400 Subject: [PATCH 6/7] x280 coreboot defconfig: t480-derived defconfig Signed-off-by: Thierry Laurion --- config/coreboot-x280-maximized.config_defconfig | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/config/coreboot-x280-maximized.config_defconfig b/config/coreboot-x280-maximized.config_defconfig index ab64ac13e..44b8273ca 100644 --- a/config/coreboot-x280-maximized.config_defconfig +++ b/config/coreboot-x280-maximized.config_defconfig @@ -1,4 +1,7 @@ -CONFIG_LOCALVERSION="Heads-" +CONFIG_BOOTSPLASH_IMAGE=y +CONFIG_BOOTSPLASH_FILE="@BRAND_DIR@/bootsplash.jpg" +CONFIG_BOOTSPLASH_CONVERT=y +CONFIG_BOOTSPLASH_CONVERT_QUALITY=90 CONFIG_VENDOR_LENOVO=y CONFIG_CBFS_SIZE=0xEEC000 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EOL_x280-maximized" @@ -7,9 +10,15 @@ CONFIG_ME_BIN_PATH="@BLOB_DIR@/xx80/x280_me.bin" CONFIG_GBE_BIN_PATH="@BLOB_DIR@/xx80/x280_gbe.bin" CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_LENOVO_X280=y -CONFIG_LINUX_COMMAND_LINE="console=tty0 loglevel=7" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM=y +CONFIG_PCIEXP_HOTPLUG=y +# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_HAVE_ME_BIN=y CONFIG_HAVE_GBE_BIN=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_BOOTSPLASH=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y CONFIG_PAYLOAD_LINUX=y CONFIG_PAYLOAD_FILE="@BOARD_BUILD_DIR@/bzImage" CONFIG_LINUX_INITRD="@BOARD_BUILD_DIR@/initrd.cpio.xz" From 689bae5dc3e19320ed5c74f2a83a9d3cfd09a1c1 Mon Sep 17 00:00:00 2001 From: Nobody <85618214+NobodyNo0ne@users.noreply.github.com> Date: Thu, 27 Aug 2026 19:38:16 +0000 Subject: [PATCH 7/7] Potential fix for pull request finding Oops Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com> Signed-off-by: Nobody <85618214+NobodyNo0ne@users.noreply.github.com> --- blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh b/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh index 16e9314c1..86e5ff012 100755 --- a/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh +++ b/blobs/xx80/x280_download_clean_deguard_me_pad_tb.sh @@ -11,10 +11,8 @@ ME_pch="LP" TBFW_SIZE=1048575 # Integrity checks for the vendor provided ME blob... -ME_DOWNLOAD_HASH="ddfbc51430699e0dfcb24a60bcb5b6e5481b325ebecf1ac177e069013189e4b0" # ...and the cleaned and deguarded version from that blob. -# DEGUARDED_ME_BIN_HASH="404e08c7c9a4fd43c3b4da82012340ae360b3fbe299f4cb6b75344054d5fc936" -DEGUARDED_ME_BIN_HASH="6f1221c936a1bed60c057883d231d48ef23c4fa9" +DEGUARDED_ME_BIN_HASH="404e08c7c9a4fd43c3b4da82012340ae360b3fbe299f4cb6b75344054d5fc936" # Integrity checks for the vendor provided Thunderbolt blob... # still not sure it'll work TB_DOWNLOAD_HASH="dcefadd999684d13a7909ee0bac17964209a6c4e6ebf5609ba72f9dab5e1d5b5"