We, as contributors and maintainers, pledge to make participation in this project a respectful, welcoming, and collaborative experience for everyone, regardless of age, experience level, nationality, gender, identity, or background.
Our goal is to foster an open and positive environment where ideas can be shared constructively and everyone is treated with professionalism and respect.
Examples of behavior that contribute to a positive environment include:
- Being respectful and courteous.
- Providing constructive feedback.
- Accepting suggestions and different viewpoints.
- Collaborating openly with others.
- Writing clear documentation and well-structured code.
- Helping improve the project through meaningful contributions.
Examples of unacceptable behavior include:
- Harassment or personal attacks.
- Disrespectful or offensive language.
- Sharing confidential information without permission.
- Spamming or intentionally disrupting discussions.
- Submitting plagiarized or malicious code.
Contributors are expected to:
- Follow Verilog HDL coding standards.
- Test changes before submitting them.
- Keep documentation up to date.
- Use meaningful commit messages.
- Respect the project's folder structure and naming conventions.
If you encounter inappropriate behavior or have concerns regarding contributions, please open a GitHub Issue or contact the project maintainer.
When reporting an issue, include:
- A clear description of the problem.
- Relevant screenshots or logs (if applicable).
- Steps to reproduce the issue.
This Code of Conduct applies to all areas of the project, including:
- Source code
- Documentation
- GitHub Issues
- Pull Requests
- Discussions
All contributors are expected to follow these guidelines whenever they interact within the project.
Project maintainers reserve the right to remove, edit, or reject contributions that do not align with this Code of Conduct.
Repeated violations may result in restrictions on future contributions.
This Code of Conduct is inspired by common open-source community standards and adapted for this academic FPGA project.
Thank you for helping make this project welcoming, professional, and collaborative.