Skip to content

CONTRIBUTING.md

Latest commit

 

History

History
215 lines (142 loc) · 3.88 KB

CONTRIBUTING.md

File metadata and controls

215 lines (142 loc) · 3.88 KB
Raw

Contributing

Thank you for your interest in contributing to the Adaptive Communication System Using Dynamic Function eXchange (DFX) project. Contributions are welcome and appreciated.

Whether you are fixing bugs, improving documentation, optimizing the Verilog modules, or adding new communication techniques, your contributions help improve this project.

How to Contribute

1. Fork the Repository

Click the Fork button on GitHub to create your own copy of the repository.

2. Clone Your Fork

git clone https://github.com/partialHuman/Adaptive-Communication-System-Using-Dynamic-Function-eXchange.git

3. Create a New Branch

Create a new branch for your feature or bug fix.

git checkout -b feature/your-feature-name

Examples:

git checkout -b feature/qpsk-module
git checkout -b bugfix/reset-signal

4. Make Your Changes

You may contribute by:

  • Improving Verilog HDL modules
  • Optimizing FPGA resource utilization
  • Adding new modulation techniques
  • Improving documentation
  • Updating hardware demonstrations
  • Fixing bugs
  • Improving simulation testbenches

5. Test Your Changes

Before submitting, verify that:

  • The project synthesizes successfully.
  • Implementation completes without errors.
  • Timing constraints are met.
  • Simulation passes.
  • Hardware functionality remains correct.
  • Documentation is updated if necessary.

6. Commit Your Changes

Use meaningful commit messages.

Example:

git add .
git commit -m "Add QPSK reconfigurable module"

or

git commit -m "Fix serializer reset logic"

7. Push Your Changes

git push origin feature/your-feature-name

8. Create a Pull Request

Open a Pull Request (PR) against the main branch.

Please include:

  • Description of the changes
  • Motivation for the changes
  • Screenshots (if applicable)
  • Simulation results (if applicable)
  • Hardware verification details (if applicable)

Project Coding Guidelines

Verilog HDL

  • Use meaningful module names.
  • Follow consistent indentation.
  • Use descriptive signal names.
  • Comment important logic.
  • Keep modules modular and reusable.

Example:

always @(posedge clk)
begin
    if (rst)
        counter <= 0;
    else
        counter <= counter + 1;
end

Documentation

If your contribution changes the design, please update the relevant documentation in the docs/ directory.

Examples include:

  • Project_Overview.md
  • Installation_Guide.md
  • Design_Flow.md
  • Results.md
  • README.md

Folder Structure

Please place new files in the appropriate directories.

src/            Verilog source files
constraints/    XDC files
simulation/     Testbenches and waveforms
reports/        Vivado reports
images/         Figures and screenshots
docs/           Documentation
bitstreams/     Generated bitstreams

Reporting Issues

If you find a bug, please create a GitHub Issue and include:

  • Problem description
  • Steps to reproduce
  • Expected behavior
  • Actual behavior
  • Vivado version
  • FPGA board used
  • Error messages or screenshots

Feature Requests

Feature requests are welcome.

Possible future enhancements include:

  • QPSK implementation
  • QAM implementation
  • OFDM communication
  • ICAP/PCAP-based partial reconfiguration
  • Software Defined Radio (SDR) integration
  • AI-based adaptive modulation
  • Performance analysis (BER, throughput, latency)

Code of Conduct

Please be respectful and constructive when contributing.

  • Be polite and professional.
  • Welcome feedback and collaboration.
  • Focus on technical improvements.
  • Respect different viewpoints.

License

By contributing to this repository, you agree that your contributions will be licensed under the same MIT License as this project.

Thank you for contributing to the Adaptive Communication System Using Dynamic Function eXchange (DFX) project!