From 00dae56aaef42d79b0e8708c5a4c0814698edd39 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 20 Jul 2026 11:08:44 +0200 Subject: [PATCH 1/2] system(c0) update STM32C0xx HAL Drivers to v1.4.1 Included in STM32CubeC0 FW v1.4.1 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 52 +- .../Inc/stm32c0xx_hal_adc.h | 8 +- .../Inc/stm32c0xx_hal_gpio_ex.h | 10 +- .../Inc/stm32c0xx_hal_hcd.h | 6 + .../Inc/stm32c0xx_hal_i2s.h | 4 +- .../Inc/stm32c0xx_hal_pcd.h | 6 +- .../Inc/stm32c0xx_hal_rcc.h | 24 +- .../Inc/stm32c0xx_hal_smartcard.h | 6 +- .../Inc/stm32c0xx_hal_spi.h | 26 +- .../Inc/stm32c0xx_hal_tim.h | 45 +- .../Inc/stm32c0xx_hal_uart.h | 2 +- .../Inc/stm32c0xx_hal_usart.h | 12 +- .../Inc/stm32c0xx_ll_adc.h | 751 +++++++++--------- .../Inc/stm32c0xx_ll_dmamux.h | 2 +- .../Inc/stm32c0xx_ll_rcc.h | 14 +- .../Inc/stm32c0xx_ll_rtc.h | 10 +- .../Inc/stm32c0xx_ll_spi.h | 47 +- .../Inc/stm32c0xx_ll_tim.h | 10 +- .../Inc/stm32c0xx_ll_usb.h | 48 +- .../Drivers/STM32C0xx_HAL_Driver/LICENSE.md | 2 +- system/Drivers/STM32C0xx_HAL_Driver/README.md | 4 +- .../STM32C0xx_HAL_Driver/Release_Notes.html | 452 +++++------ .../STM32C0xx_HAL_Driver/SW_Security_Level.md | 47 ++ .../STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c | 20 +- .../Src/stm32c0xx_hal_dma.c | 4 - .../Src/stm32c0xx_hal_flash.c | 18 +- .../Src/stm32c0xx_hal_flash_ex.c | 2 +- .../Src/stm32c0xx_hal_hcd.c | 119 +-- .../Src/stm32c0xx_hal_i2s.c | 4 +- .../Src/stm32c0xx_hal_pcd.c | 138 +--- .../Src/stm32c0xx_hal_pcd_ex.c | 25 +- .../Src/stm32c0xx_hal_rcc.c | 12 +- .../Src/stm32c0xx_hal_smartcard.c | 16 +- .../Src/stm32c0xx_hal_spi.c | 297 +++---- .../Src/stm32c0xx_hal_tim.c | 87 +- .../Src/stm32c0xx_hal_tim_ex.c | 12 +- .../Src/stm32c0xx_hal_timebase_tim_template.c | 14 + .../Src/stm32c0xx_hal_uart.c | 62 +- .../Src/stm32c0xx_ll_rtc.c | 3 +- .../Src/stm32c0xx_ll_spi.c | 7 +- .../Src/stm32c0xx_ll_tim.c | 12 +- .../Src/stm32c0xx_ll_usb.c | 120 +-- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 43 files changed, 1317 insertions(+), 1245 deletions(-) create mode 100644 system/Drivers/STM32C0xx_HAL_Driver/SW_Security_Level.md diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index ef8d28c9db..4d74b02000 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -361,7 +361,9 @@ extern "C" { #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -564,6 +566,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -1485,7 +1490,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1912,7 +1917,11 @@ extern "C" { #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define PWR_PVM_USB PWR_PVM_ENABLE +#define PWR_FLAG_PVMOUSB PWR_FLAG_PVMOVDDIO2 +#define PWR_FLAG_PVMO_USB PWR_FLAG_PVMO_VDDIO2 +#endif /* STM32G0C1xx || STM32G0B1xx */ #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING @@ -2025,6 +2034,9 @@ extern "C" { #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif +#if defined (STM32H7RS) +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO PWR_SMPS_1V8_SUPPLIES_EXT_VDD_SUPPLIES_LDO +#endif /** * @} @@ -2146,6 +2158,20 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + +#if defined(STM32N6) +/* alias CMSIS */ +#define CSI_PCR_PWRDOWN_Pos CSI_PCR_NPWRDOWN_Pos +#define CSI_PCR_PWRDOWN_Msk CSI_PCR_NPWRDOWN_Msk +#define CSI_PCR_PWRDOWN CSI_PCR_NPWRDOWN +#endif /* STM32N6 */ + /** * @} */ @@ -3671,8 +3697,14 @@ extern "C" { #define RCC_PLLDIV_3 RCC_PLL_DIV3 #define RCC_PLLDIV_4 RCC_PLL_DIV4 +#if !defined (STM32WL4) #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#endif + + #define RCC_MCO_NODIV RCC_MCODIV_1 #define RCC_MCO_DIV1 RCC_MCODIV_1 #define RCC_MCO_DIV2 RCC_MCODIV_2 @@ -3685,11 +3717,9 @@ extern "C" { #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 @@ -3698,8 +3728,14 @@ extern "C" { #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK #endif +#if defined(STM32C0) +#define RCC_LSEDRIVE_LOW RCC_LSEDRIVE_MEDIUMHIGH +#define RCC_LSEDRIVE_MEDIUMLOW RCC_LSEDRIVE_MEDIUMHIGH +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3950,8 +3986,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \ - defined (STM32U0) || defined (STM32U3) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \ + defined (STM32U0) || defined (STM32U3) || defined (STM32WL4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h index 07388f88e7..344d76c4b1 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h @@ -1410,7 +1410,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval Value between Min_Data=0 and Max_Data=18 */ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ @@ -1458,7 +1458,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. */ #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) @@ -1515,7 +1515,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval Value "0" if the channel corresponds to a parameter definition of a * ADC external channel (channel connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of @@ -1572,7 +1572,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval Returned value can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h index c7215053cc..ebc92fd864 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_gpio_ex.h @@ -61,9 +61,9 @@ extern "C" { #define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ #define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ #endif /* !STM32C011xx */ -#if defined(STM32C031xx) || defined(STM32C071xx) || defined(STM32C091xx) || defined(STM32C092xx) +#if defined(STM32C031xx) || defined(STM32C051xx) || defined(STM32C071xx) || defined(STM32C091xx) || defined(STM32C092xx) #define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ -#endif /* STM32C031xx | STM32C071xx | STM32C091xx | STM32C092xx*/ +#endif /* STM32C031xx | STM32C051xx | STM32C071xx | STM32C091xx | STM32C092xx*/ #if defined(SPI2) #define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ #endif /* SPI2 */ @@ -195,6 +195,9 @@ extern "C" { */ #define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ #define GPIO_AF7_I2C1 ((uint8_t)0x07) /*!< I2C1 Alternate Function mapping */ +#if defined(USART3) +#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ +#endif /* USART3 */ /** * @brief AF 8 selection */ @@ -255,6 +258,9 @@ extern "C" { */ #define GPIO_AF13_TIM14 ((uint8_t)0x0D) /*!< TIM14 Alternate Function mapping */ #define GPIO_AF13_TIM3 ((uint8_t)0x0D) /*!< TIM3 Alternate Function mapping */ +#if defined(FDCAN1) +#define GPIO_AF13_FDCAN1 ((uint8_t)0x0D) /*!< FDCAN1 Alternate Function mapping */ +#endif /* FDCAN1 */ /** * @brief AF 14 selection diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_hcd.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_hcd.h index f853e297e0..d365a14211 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_hcd.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_hcd.h @@ -126,6 +126,9 @@ typedef struct /** @defgroup HCD_Exported_Constants HCD Exported Constants * @{ */ +#ifndef HAL_HCD_CHANNEL_NAK_COUNT +#define HAL_HCD_CHANNEL_NAK_COUNT 2U +#endif /* HAL_HCD_CHANNEL_NAK_COUNT */ /** @defgroup HCD_Speed HCD Speed * @{ @@ -151,6 +154,8 @@ typedef struct */ #define HCD_PHY_ULPI 1U #define HCD_PHY_EMBEDDED 2U +#define HCD_HS_PHY_EMBEDDED 3U +#define HCD_PHY_UTMI 3U /** * @} */ @@ -205,6 +210,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num); HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_i2s.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_i2s.h index 3cfb8a4826..aebdf87260 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_i2s.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_i2s.h @@ -452,8 +452,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h index 2b04997806..b352271407 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_pcd.h @@ -104,7 +104,7 @@ typedef struct uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; - + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE */ @@ -159,6 +159,7 @@ typedef struct */ #define PCD_PHY_ULPI 1U #define PCD_PHY_EMBEDDED 2U +#define PCD_HS_PHY_EMBEDDED 3U #define PCD_PHY_UTMI 3U /** * @} @@ -198,7 +199,6 @@ typedef struct #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE) - /** * @} */ @@ -361,7 +361,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); */ -#define USB_WAKEUP_EXTI_LINE (0x1U << 4) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_WAKEUP_EXTI_LINE (0x1UL << 4) /*!< USB FS EXTI Line WakeUp Interrupt */ /** diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h index 588ba84bb5..9295de75e2 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_rcc.h @@ -508,31 +508,31 @@ typedef struct /* @endcond */ #define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ - (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) #define RCC_MCO1_PA9 (RCC_MCO1_INDEX |\ - (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) #define RCC_MCO1_PF2 (RCC_MCO1_INDEX |\ - (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) #define RCC_MCO1 RCC_MCO1_PA8 /*!< Alias for compatibility */ #define RCC_MCO2_PA8 (RCC_MCO2_INDEX |\ - (GPIO_AF15_MCO2 << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF15_MCO2 << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) #define RCC_MCO2_PA10 (RCC_MCO2_INDEX |\ - (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) #define RCC_MCO2_PA14 (RCC_MCO2_INDEX |\ - (GPIO_AF11_MCO2 << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF11_MCO2 << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_14) #if !defined(STM32C011xx) #define RCC_MCO2_PA15 (RCC_MCO2_INDEX |\ - (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_15) #define RCC_MCO2_PB2 (RCC_MCO2_INDEX |\ - (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ + ((uint32_t)GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | \ (GPIO_GET_INDEX(GPIOB) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) #endif /* STM32C011xx */ #define RCC_MCO2 RCC_MCO2_PA10 /*!< Alias for compatibility */ @@ -666,10 +666,8 @@ typedef struct /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration * @{ */ -#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< LSE high drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH 0x00000000U /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< LSE high drive capability */ /** * @} */ @@ -1967,8 +1965,6 @@ typedef struct * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: - * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. * @retval None diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_smartcard.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_smartcard.h index 7a8786f366..7c8d308a61 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_smartcard.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_smartcard.h @@ -725,13 +725,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h index ed2f5aba32..4a1e523488 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_spi.h @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h index d4a7d38d1b..8b59e69770 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_tim.h @@ -1134,7 +1134,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Break_System TIM Break System * @{ */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIM1/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIM1/15/16/17 */ /** * @} */ @@ -1752,7 +1752,8 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} @@ -2124,20 +2125,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -2151,16 +2147,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) /** * @} diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h index 91f6c6342a..509c46cee2 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_uart.h @@ -1278,7 +1278,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U) /** @brief Check UART assertion time. * @param __TIME__ 5-bit value assertion time. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_usart.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_usart.h index 0d6a837038..430ce550b8 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_usart.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_usart.h @@ -549,10 +549,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -574,10 +574,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h index 40edaef634..b244c741d4 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h @@ -268,7 +268,7 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF756AUL)) /* Internal voltage reference, address of +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x1FFF756AUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) @@ -282,7 +282,7 @@ extern "C" { by TEMPSENSOR_CAL1_ADDR (with taking into account conversion from digital value resolution 12 bit, analog voltage reference ratio between calibration and application environments) */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7568UL)) /* Internal temperature sensor, address of +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x1FFF7568UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32C0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ @@ -790,6 +790,11 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#if defined(TIM15) +#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM15 TRGO. + Trigger edge set to rising edge (default setting). */ +#endif /* TIM15 */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. @@ -1290,33 +1295,33 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * number is returned, either defined with number * or with bitfield (only one bit must be set). * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -1324,7 +1329,7 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ @@ -1366,33 +1371,33 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * will return a data equivalent to "LL_ADC_CHANNEL_4". * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -1400,7 +1405,7 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ @@ -1424,33 +1429,33 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -1458,7 +1463,7 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel * (channel connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. @@ -1480,33 +1485,33 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * or a value from functions where a channel number is returned * from ADC registers. * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -1514,7 +1519,7 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1581,33 +1586,33 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * ADC1, LL_ADC_AWD1, * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -1615,7 +1620,7 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @param __GROUP__ This parameter can be one of the following values: * @arg @ref LL_ADC_GROUP_REGULAR * @retval Returned value can be one of the following values: @@ -1648,7 +1653,7 @@ and auto power-off combined. See description with function @ref LL_ADC_SetLowPow * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG * @arg @ref LL_ADC_AWD_CH_VDDA_REG * @arg @ref LL_ADC_AWD_CH_VSSA_REG - * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. + * (1) On STM32C0, parameter not available on STM32C011xx. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) @@ -3048,33 +3053,33 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 * @param Channel This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3082,7 +3087,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) @@ -3136,33 +3141,33 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3170,7 +3175,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { @@ -3238,33 +3243,33 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, u * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3272,7 +3277,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, u * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) @@ -3339,33 +3344,33 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3373,7 +3378,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) @@ -3440,33 +3445,33 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Ch * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3474,7 +3479,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Ch * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) @@ -3531,33 +3536,33 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels * @param ADCx ADC instance * @retval Returned value can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3565,7 +3570,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) { @@ -3797,33 +3802,33 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3831,7 +3836,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @param SamplingTimeY This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 @@ -3876,33 +3881,33 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 (1) + * @arg @ref LL_ADC_CHANNEL_9 (1) + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (3) + * @arg @ref LL_ADC_CHANNEL_18 (3) + * @arg @ref LL_ADC_CHANNEL_19 (3) + * @arg @ref LL_ADC_CHANNEL_20 (3) + * @arg @ref LL_ADC_CHANNEL_21 (3) + * @arg @ref LL_ADC_CHANNEL_22 (3) + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VDDA (2) + * @arg @ref LL_ADC_CHANNEL_VSSA (2) * * (1) On STM32C0, parameter can be set in ADC group sequencer * only if sequencer is set in mode "not fully configurable", @@ -3910,7 +3915,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * (2) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. + * (3) ADC channels not available on STM32C011xx device. * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 @@ -3924,7 +3929,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) - & 0x1FUL)); + & 0x1FUL)) & 0x01UL; /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) @@ -3998,7 +4003,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG * @arg @ref LL_ADC_AWD_CH_VDDA_REG * @arg @ref LL_ADC_AWD_CH_VSSA_REG - * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. + * (1) On STM32C0, parameter not available on STM32C011xx. * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) @@ -4007,7 +4012,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg; + __IO uint32_t *preg; if (AWDy == LL_ADC_AWD1) { @@ -4109,15 +4114,15 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG * @arg @ref LL_ADC_AWD_CH_VDDA_REG * @arg @ref LL_ADC_AWD_CH_VSSA_REG - * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. + * (1) On STM32C0, parameter not available on STM32C011xx. */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h index 874de099e3..4afeee6add 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_dmamux.h @@ -247,7 +247,7 @@ extern "C" { #define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ #define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ #define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ -#define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from TIM14 OC */ +#define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from TIM14 OC */ /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h index 24550fcedb..565a0ca842 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h @@ -181,10 +181,12 @@ typedef struct /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability * @{ */ -#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< Xtal mode higher driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH 0x00000000U /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< Xtal mode higher driving capability */ + +/* Aliases */ +#define LL_RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_MEDIUMHIGH +#define LL_RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMHIGH /** * @} */ @@ -956,8 +958,6 @@ __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) * @note The oscillator is in Xtal mode when it is not in bypass mode. * @rmtoll CSR1 LSEDRV LL_RCC_LSE_SetDriveCapability * @param LSEDrive This parameter can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH * @arg @ref LL_RCC_LSEDRIVE_HIGH * @retval None @@ -971,8 +971,6 @@ __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) * @brief Get LSE oscillator drive capability * @rmtoll CSR1 LSEDRV LL_RCC_LSE_GetDriveCapability * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH * @arg @ref LL_RCC_LSEDRIVE_HIGH */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rtc.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rtc.h index 487aa54b5d..277e4abbee 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rtc.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rtc.h @@ -1074,7 +1074,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | \ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ @@ -1102,7 +1102,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | \ @@ -1407,7 +1407,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) { - register uint32_t temp; + uint32_t temp; temp = (WeekDay << RTC_DR_WDU_Pos) | \ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ @@ -1435,7 +1435,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ @@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h index 5313c814ed..ba464ca9cb 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -2252,7 +2267,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) */ ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx,const LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h index ed61e872d8..26d7893b08 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_tim.h @@ -31,7 +31,13 @@ extern "C" { * @{ */ -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) +#if defined (TIM1) \ + || defined (TIM2) \ + || defined (TIM3) \ + || defined (TIM14) \ + || defined (TIM15) \ + || defined (TIM16) \ + || defined (TIM17) /** @defgroup TIM_LL TIM * @{ @@ -143,7 +149,7 @@ static const uint8_t SHIFT_TAB_OISx[] = */ #define OCREF_CLEAR_SELECT_POS (16U) -#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x00010000 */ +#define OCREF_CLEAR_SELECT_MSK (0x1UL << OCREF_CLEAR_SELECT_POS) /*!< 0x00010000 */ /** * @} */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usb.h b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usb.h index 2cf6f309cc..58a2cb14e0 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usb.h +++ b/system/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_usb.h @@ -51,6 +51,7 @@ typedef enum USB_HOST_MODE = 1 } USB_ModeTypeDef; +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief URB States definition */ @@ -61,7 +62,8 @@ typedef enum URB_NOTREADY, URB_NYET, URB_ERROR, - URB_STALL + URB_STALL, + URB_NAK_WAIT } USB_URBStateTypeDef; /** @@ -80,6 +82,7 @@ typedef enum HC_BBLERR, HC_DATATGLERR } USB_HCStateTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** @@ -122,6 +125,7 @@ typedef struct uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ } USB_CfgTypeDef; +#if defined (HAL_PCD_MODULE_ENABLED) typedef struct { uint8_t num; /*!< Endpoint number @@ -166,7 +170,9 @@ typedef struct uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ } USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ +#if defined (HAL_HCD_MODULE_ENABLED) typedef struct { uint8_t dev_addr; /*!< USB device address. @@ -232,13 +238,20 @@ typedef struct USB_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_HCStateTypeDef */ } USB_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) typedef USB_EPTypeDef USB_DRD_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /* Exported constants --------------------------------------------------------*/ @@ -337,8 +350,8 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; * @} */ /******************** Bit definition for USB_COUNTn_RX register *************/ -#define USB_CNTRX_NBLK_MSK (0x1FU << 26) -#define USB_CNTRX_BLSIZE (0x1U << 31) +#define USB_CNTRX_NBLK_MSK (0x1FUL << 26) +#define USB_CNTRX_BLSIZE (0x1UL << 31) /*Set Channel/Endpoint to the USB Register */ @@ -683,21 +696,21 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ do { \ uint32_t wNBlocks; \ - \ - (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ + uint32_t wRegVal = (uint32_t)(pdwReg) & ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ \ if ((wCount) == 0U) \ { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ + wRegVal |= USB_CNTRX_BLSIZE; \ } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2(wRegVal, (wCount), wNBlocks); \ } \ else \ { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK32(wRegVal, (wCount), wNBlocks); \ } \ + (pdwReg) = wRegVal; \ } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ @@ -866,17 +879,23 @@ uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); -HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); -uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); -HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); +#if defined (HAL_HCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num); +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num); +HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); +HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); + +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); + HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); @@ -907,5 +926,4 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, } #endif /* __cplusplus */ - #endif /* STM32C0xx_LL_USB_H */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/LICENSE.md b/system/Drivers/STM32C0xx_HAL_Driver/LICENSE.md index 4a464d09d0..b14e2a70b4 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/LICENSE.md +++ b/system/Drivers/STM32C0xx_HAL_Driver/LICENSE.md @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32C0xx_HAL_Driver/README.md b/system/Drivers/STM32C0xx_HAL_Driver/README.md index d8fa67c536..5d5691c56d 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/README.md +++ b/system/Drivers/STM32C0xx_HAL_Driver/README.md @@ -1,6 +1,6 @@ # STM32CubeC0 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32c0xx_hal_driver.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.4.1-brightgreen.svg) ## Overview @@ -33,4 +33,4 @@ The full **STM32CubeC0** MCU package is available [here](https://github.com/STMi ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html index 22393d9c22..eb2eda7e21 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32C0xx_HAL_Driver/Release_Notes.html @@ -5,92 +5,169 @@ Release Notes for STM32CubeC0 HAL and LL drivers - - +
-

Release Notes -for STM32CubeC0 HAL and LL drivers

+

Release Notes for STM32CubeC0 HAL and LL drivers

Copyright ©  2022 STMicroelectronics

- +

Purpose

-

The STM32Cube HAL and LL, an STM32 abstraction layer embedded -software, ensure maximized portability across STM32 portfolio.

-

The portable APIs layer provides a generic, multi instanced and -simple set of APIs to interact with the upper layer (application, -libraries and stacks). It is composed of native and extended APIs set. -It is directly built around a generic architecture and allows the -build-upon layers, like the middleware layer, to implement its functions -without knowing in-depth the used STM32 device. This improves the -library code reusability and guarantees an easy portability on other -devices and STM32 families.

-

The Low Layer (LL) drivers are part of the STM32Cube firmware HAL -that provides a basic set of optimized and one-shot services. The Low -layer drivers, contrary to the HAL ones are not fully portable across -the STM32 families; the availability of some functions depends on the -physical availability of the relative features on the product. The Low -Layer (LL) drivers are designed to offer the following features:

-
    -
  • New set of inline functions for direct and atomic register -access
    • -
  • One-shot operations that can be used by the HAL drivers or from -application level
    • -
  • Full independence from HAL and standalone usage (without HAL -drivers)
    • +

    The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

    +

    The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

    +

    The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one-shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

    +
      +
    • New set of inline functions for direct and atomic register access
      • +
    • One-shot operations that can be used by the HAL drivers or from application level
      • +
    • Full independence from HAL and standalone usage (without HAL drivers)
    • Full features coverage of all the supported peripherals
-
-

Update History

+
+

Update History

- - +

Main Changes

    -
  • Maintenance Release of STM32CubeC0 HAL/LL Drivers supporting -STM32C011xx/C031xx/C051xx/C071xx/C091xx/C092xx -devices
    • -
  • General updates to fix known defects and implementation -enhancements
    • +
  • General updates to fix known defects and implementation enhancements

HAL Drivers updates

    +
  • General updates to fix known defects and implementation enhancements
    • +
  • HAL Generic driver: +
      +
    • Update HAL_SetTickFreq() API to restore current tick frequency when call to HAL_InitTick() API fails
      • +
    • Fix the timer timebase initialization sequence by registering the callback before starting the timer, ensuring proper callback handling in FreeRTOS projects
      • +
    • Fix Misra C 2012 Rule 12.2 violation
      • +
    • +
  • HAL RCC driver +
      +
    • Update HAL_RCC_MCOConfig() API documentation to clarify the available MCOx pins
      • +
    • Remove unsupported LSE drive capability definitions from the RCC drive
      • +
    • Fix Misra C 2012 Rule 12.2 violation
      • +
    • +
  • HAL GPIO driver: +
      +
    • Add GPIO_AF13_FDCAN1, GPIO_AF7_USART3 and GPIO_AF0_USART2 macros
      • +
    • +
  • HAL FLASH driver: +
      +
    • Improve timeout handling in FLASH_WaitForLastOperation() function by updating the timeout calculation method
      • +
    • +
  • HAL DMA driver: +
      +
    • Correct tim14_trgo assignment definition to be aligned with the latest Reference Manual
      • +
    • Remove HAL_LOCK/HAL_UNLOCK call from HAL_DMA_Abort_IT() API to avoid DMA handle from being blocked in “locked” state
      • +
    • +
  • LL ADC driver +
      +
    • Fix LL_ADC_GetChannelSamplingTime() API when multiple channels configured and the lowest channel number is queried.
      • +
    • Remove deprecated ‘register’ keyword to avoid GCC compiler issue
      • +
    • Add the define related to the external trigger from TIM15 TRGO
      • +
    • Add const qualifier for calibrated values
      • +
    • +
  • LL RTC driver: +
      +
    • Remove deprecated ‘register’ keyword to avoid GCC compiler issue
      • +
    • Add instruction to clear RTC CR register in LL_RTC_DeInit() API to complete the deinitialization sequence
      • +
    • +
  • LL TIM driver: +
      +
    • Remove Channel 2 enable from LL_TIM_HALLSENSOR_Init() API.
      • +
    • +
  • HAL/LL SPI driver: +
      +
    • Add a note to clarify HAL_SPI_Receive() API behavior in master mode
      • +
    • Add units to physical measurements
      • +
    • Prevent buffer overflow in SPI_WaitFifoStateUntilTimeout() function
      • +
    • Add a data size check before changing state in the reception API.
      • +
    • Fix INTEGER_OVERFLOW Coverity warning
      • +
    • Prevent unaligned access in SPI ISR register
      • +
    • Remove data packing, which is not supported by Cortex.
      • +
    • Fix Misra C 2012 Rule 8.13 violation
      • +
    • +
  • HAL USART driver: +
      +
    • Fix Misra C 2012 Rule 12.2 violation
      • +
    • +
  • HAL UART driver: +
      +
    • Align UART baud rate macros definition between LL and HAL
      • +
    • Fix transfer count underflow in polling mode
      • +
    • Fix transfer count handling in DMA linked-list mode
      • +
    • Remove the call to the __HAL_UART_DISABLE() macro from the HAL_UART_DeInit() API.
      • +
    • +
  • HAL LPUART driver: +
      +
    • Fix transfer count underflow in polling mode
      • +
    • +
  • HAL I2S driver: +
      +
    • Fix Misra C 2012 Rule 8.13 violation
      • +
    • +
  • HAL SMARTCARD driver +
      +
    • Fix Misra C 2012 Rule 12.2 violation
      • +
    • Update the configuration sequence to better comply with SMARTCARD specifications
      • +
    • +
  • HAL/LL USB driver: +
      +
    • Security Advisory SA0035 fixed (driver buffer overflow issues)
      • +
    • Add a note into the “How to use” section about macro USE_USB_DOUBLE_BUFFER and the possibility to reduce the driver’s memory footprint
      • +
    • Fix Misra C 2012 Rule 2.3 violation
      • +
    • Ensure NYET/NAK Interrupts are enabled
      • +
    • Remove __HAL_LOCK() from HAL_Callbacks APIs in hal_pcd and hal_hcd drivers
      • +
    • Activate the scatter gather mode constraint
      • +
    • Rework port device connect/disconnect in HCD_Port_IRQHandler() function
      • +
    • Add HCD_HS_PHY_EMBEDDED and HCD_PHY_UTMI macros
      • +
    • Update PCD_EP_ISR_Handler() function to avoid out-of-bound possible read
      • +
    • Fix USB_DRD_SET_CHEP_CNT_RX_REG macro to update COUNTn_RX register in single operation
      • +
    • Add get frame number support
      • +
    • +
+

Note: HAL/LL Backward compatibility ensured by legacy defines.

+

Known Limitations

+
    +
  • None
    • +
+

Backward Compatibility

+
    +
  • Not applicable
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Maintenance Release of STM32CubeC0 HAL/LL Drivers supporting STM32C011xx/C031xx/C051xx/C071xx/C091xx/C092xx devices
    • +
  • General updates to fix known defects and implementation enhancements
    • +
+

HAL Drivers updates

+
  • HAL ADC driver:
    • Change ADC calibration procedure
  • HAL RCC driver:
      -
    • Add notes to highlight HSI48 clock division factor update limitation -when HSI48 oscillator is selected as system clock
      • +
    • Add notes to highlight HSI48 clock division factor update limitation when HSI48 oscillator is selected as system clock
  • HAL TIM driver:
      @@ -98,46 +175,37 @@

      HAL Drivers updates

  • HAL UART driver:
      -
    • Correct references to HAL_UARTEx_WakeupCallback and to -HAL_UART_WAKEUP_CB_ID define, according to serie capabilities
      • -
    • Provide accurate position in RxEventCallback when ReceptionToIdle -mode is used with DMA, when UART and DMA interrupts process is -delayed
      • +
    • Correct references to HAL_UARTEx_WakeupCallback and to HAL_UART_WAKEUP_CB_ID define, according to series capabilities
      • +
    • Provide accurate position in RxEventCallback when ReceptionToIdle mode is used with DMA, when UART and DMA interrupts process is delayed

LL Drivers updates

  • LL USART driver:
      -
    • Solve Coverity out-of-bound memory access warning in use of -USART_PRESCALER_TAB array
      • +
    • Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • None
-

Backward Compatibility

+

Backward Compatibility

  • Not applicable
- - +
-

Main Changes

+

Main Changes

    -
  • Official Release of STM32CubeC0 Firmware package supporting -STM32C051xx and STM32C091/92xx -devices
    • -
  • General updates to fix known defects and implementation -enhancements
    • +
  • Official Release of STM32CubeC0 Firmware package supporting STM32C051xx and STM32C091/92xx devices
    • +
  • General updates to fix known defects and implementation enhancements
-

HAL Drivers updates

+

HAL Drivers updates

  • HAL generic driver:
      @@ -158,8 +226,7 @@

      HAL Drivers updates

  • HAL I2C driver:
      -
    • Update function HAL_I2C_IsDeviceReady() to take into account the -number of trials
      • +
    • Update function HAL_I2C_IsDeviceReady() to take into account the number of trials
    • Move the prefetch process in function HAL_I2C_Slave_Transmit
  • HAL PCD driver: @@ -168,8 +235,7 @@

    HAL Drivers updates

  • HAL RCC driver:
      -
    • Update function HAL_RCC_GetClockConfig() to take into account the -RCC_CR_SYSDIV
      • +
    • Update function HAL_RCC_GetClockConfig() to take into account the RCC_CR_SYSDIV
  • HAL SPI driver:
      @@ -177,8 +243,7 @@

      HAL Drivers updates

  • HAL UART driver:
      -
    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in -polling mode
      • +
    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode

    • LL Drivers updates

    @@ -197,47 +262,36 @@

    LL Drivers updates

    Note: HAL/LL Backward compatibility ensured by legacy defines.

    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward Compatibility

    +

    Backward Compatibility

    • Not applicable
    - - +
    -

    Main Changes

    +

    Main Changes

      -
    • Official Release of STM32CubeC0 Firmware package supporting -STM32C071xx devices
      • -
    • General updates to fix known defects and implementation -enhancements
      • +
    • Official Release of STM32CubeC0 Firmware package supporting STM32C071xx devices
      • +
    • General updates to fix known defects and implementation enhancements
    -

    HAL Drivers updates

    +

    HAL Drivers updates

    • HAL generic driver:
        -
      • Remove invalid HAL_SYSCFG_EnableIOAnalogSwitchBooster() and -HAL_SYSCFG_DisableIOAnalogSwitchBooster() APIs
        • -
      • Rename __HAL_RCC_APB1_FORCE_RESET and __HAL_RCC_APB2_FORCE_RESET -macros by __HAL_RCC_APB1_GRP1_FORCE_RESET and -__HAL_RCC_APB1_GRP2_FORCE_RESET
        • -
      • Rename __HAL_RCC_APB1_RELEASE_RESET and __HAL_RCC_APB2_RELEASE_RESET -macros by __HAL_RCC_APB1_GRP1_RELEASE_RESET and -__HAL_RCC_APB1_GRP2_RELEASE_RESET
        • +
      • Remove invalid HAL_SYSCFG_EnableIOAnalogSwitchBooster() and HAL_SYSCFG_DisableIOAnalogSwitchBooster() APIs
        • +
      • Rename __HAL_RCC_APB1_FORCE_RESET and __HAL_RCC_APB2_FORCE_RESET macros by __HAL_RCC_APB1_GRP1_FORCE_RESET and __HAL_RCC_APB1_GRP2_FORCE_RESET
        • +
      • Rename __HAL_RCC_APB1_RELEASE_RESET and __HAL_RCC_APB2_RELEASE_RESET macros by __HAL_RCC_APB1_GRP1_RELEASE_RESET and __HAL_RCC_APB1_GRP2_RELEASE_RESET
    • HAL ADC driver:
        -
      • Update HAL_ADC_IRQHandler by adding checks on ADC Ready flag and End -of Calibration flag
        • -
      • Add HAL_ADC_CalibrationCpltCallback() and HAL_ADC_ADCReadyCallback() -APIs
        • +
      • Update HAL_ADC_IRQHandler by adding checks on ADC Ready flag and End of Calibration flag
        • +
      • Add HAL_ADC_CalibrationCpltCallback() and HAL_ADC_ADCReadyCallback() APIs
      • Add ADC_FLAG_EOCAL ADC End of Calibration interrupt flag
    • HAL CORTEX driver: @@ -246,76 +300,53 @@

      HAL Drivers updates

  • HAL FLASH driver:
      -
    • Add OB_USER_HSE_NOT_REMAPPED and OB_USER_SECURE_MUXING_EN -definitions
      • +
    • Add OB_USER_HSE_NOT_REMAPPED and OB_USER_SECURE_MUXING_EN definitions
    • Update OB_USER_ALL definition
      • -
    • Add OB_HSE_NOT_REMAPPED_ENABLE and OB_HSE_NOT_REMAPPED_DISABLE FLASH -Option Bytes User HSE REMAP enable/disable definitions
      • -
    • Add OB_SECURE_MUXING_ENABLE and OB_SECURE_MUXING_DISABLE Option -Bytes User Multiple-bonding security enable/disable definitions
      • -
    • Update FLASH_PAGE_NB definition to compute the flash pages number -based on the flash size
      • +
    • Add OB_HSE_NOT_REMAPPED_ENABLE and OB_HSE_NOT_REMAPPED_DISABLE FLASH Option Bytes User HSE REMAP enable/disable definitions
      • +
    • Add OB_SECURE_MUXING_ENABLE and OB_SECURE_MUXING_DISABLE Option Bytes User Multiple-bonding security enable/disable definitions
      • +
    • Update FLASH_PAGE_NB definition to compute the flash pages number based on the flash size
  • HAL I2C driver:
      -
    • Update HAL_I2C_Slave_Transmit to check if the received NACK is the -correct one
      • -
    • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF -independently from I2C_FLAG_RXNE
      • +
    • Update HAL_I2C_Slave_Transmit to check if the received NACK is the correct one
      • +
    • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE
    • Remove the unusable code in HAL_I2C_IsDeviceReady() API
      • -
    • Remove unused state defines HAL_I2C_STATE_TIMEOUT and -HAL_I2C_STATE_ERROR in HAL_I2C_StateTypeDef
      • +
    • Remove unused state defines HAL_I2C_STATE_TIMEOUT and HAL_I2C_STATE_ERROR in HAL_I2C_StateTypeDef
    • Update I2C_WaitOnFlagUntilTimeout to handle error case.
      • -
    • Update HAL_I2C_Master_Abort_IT to support memory abort -transfer.
      • +
    • Update HAL_I2C_Master_Abort_IT to support memory abort transfer.
  • HAL I2S driver:
      -
    • Update HAL I2S driver to fix misplaced __HAL_LOCK and remove ‘go to’ -instruction
      • +
    • Update HAL I2S driver to fix misplaced __HAL_LOCK and remove ‘go to’ instruction
  • HAL SPI driver:
    • Update IT API to enable interrupts after process unlock
      • -
    • Update driver to keep state in case of error and set -HAL_SPI_STATE_READY only in case of HAL_TIMEOUT
      • -
    • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of -one byte transaction
      • +
    • Update driver to keep state in case of error and set HAL_SPI_STATE_READY only in case of HAL_TIMEOUT
      • +
    • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction
  • HAL SMBUS driver:
    • Update SMBUS_ITErrorHandler to flash TXDR only in case of error
      • -
    • Remove unused state defines HAL_SMBUS_STATE_TIMEOUT and -HAL_SMBUS_STATE_ERROR in HAL_I2C_StateTypeDef
      • +
    • Remove unused state defines HAL_SMBUS_STATE_TIMEOUT and HAL_SMBUS_STATE_ERROR in HAL_I2C_StateTypeDef
  • HAL RCC driver:
      -
    • Update HAL_RCC_GetHCLKFreq() to Compute SystemCoreClock value
      • -
    • -
  • HAL RTC driver: -
      -
    • Remove RTC_FLAG_ITSF and RTC_CLEAR_ITSF to be aligned with reference -manual
      • -
    • Remove meaningless __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, -__HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, -__HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG and -__HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG macros
      • +

    • Update HAL_RCC_GetHCLKFreq() to Compute SystemCoreClock value

      • +
    • HAL RTC driver:
      • +
    • Remove RTC_FLAG_ITSF and RTC_CLEAR_ITSF to be aligned with reference manual
      • +
    • Remove meaningless __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE, __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE, __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG and __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG macros
    • Update RTC_EXTI_LINE_TIMESTAMP_EVENT definition
      • -
    • Remove extra HAL_RTCEx_SetInternalTimeStamp() and -HAL_RTCEx_DeactivateInternalTimeStamp() definitions
      • +

    • Remove extra HAL_RTCEx_SetInternalTimeStamp() and HAL_RTCEx_DeactivateInternalTimeStamp() definitions

  • HAL TIM driver:
      -
    • Add the possibility to configure the break inputs in bidirectional -mode for lite timers
      • +
    • Add the possibility to configure the break inputs in bidirectional mode for lite timers
    • Added system break interrupt handling in IRQ handler
      • -
    • Update interrupt flag to be cleared when the update event is -generated by software
      • +
    • Update interrupt flag to be cleared when the update event is generated by software
    • Fixed some typos in code comments
      • -
    • Made HAL_TIMEx_OCN_Stop_IT and HAL_TIMEx_PWMN_Stop_IT more -generic
      • -
    • Improved HAL_TIMEx_ConfigBreakDeadTime() function -implementation
      • +
    • Made HAL_TIMEx_OCN_Stop_IT and HAL_TIMEx_PWMN_Stop_IT more generic
      • +
    • Improved HAL_TIMEx_ConfigBreakDeadTime() function implementation
    • Improved CH4N support handling
    • Fix typo in PWM symmetric mode related constants names
    • @@ -326,16 +357,10 @@

    HAL Drivers updates

  • HAL UART driver:
    • Fixed some typos in code comments
      • -
    • Remove __HAL_LOCK() from -HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback()
      • -
    • Fix incorrect gState check in -HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to -allow user Rx Event Callback registration when a transmit is -ongoing
      • -
    • Update driver to avoid RTOF flag to be cleared by a transmit process -in polling mode
      • -
    • Ensure UART Rx buffer is not written beyond boundaries in case of RX -FIFO reception in Interrupt mode
      • +
    • Remove __HAL_LOCK() from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback()
      • +
    • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing
      • +
    • Update driver to avoid RTOF flag to be cleared by a transmit process in polling mode
      • +
    • Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode

    • LL Drivers updates

    @@ -346,24 +371,19 @@

    LL Drivers updates

  • LL DMA driver:
      -
    • Add missing LL_DMAMUX_SYNC_DMAMUX_CH3, LL_DMAMUX_REQ_GEN_DMAMUX_CH3 -and LL_DMAMUX_SYNC_TIM14_OC definitions
      • +
    • Add missing LL_DMAMUX_SYNC_DMAMUX_CH3, LL_DMAMUX_REQ_GEN_DMAMUX_CH3 and LL_DMAMUX_SYNC_TIM14_OC definitions
  • LL GPIO driver:
      -
    • Update LL_GPIO_Init() to avoid causing quick switch to low level on -the pins
      • +
    • Update LL_GPIO_Init() to avoid causing quick switch to low level on the pins
  • LL RCC driver:
      -
    • Remove meaningless RCC_PLL_GetFreqDomain_SYS(), -RCC_PLL_GetFreqDomain_ADC() and RCC_PLL_GetFreqDomain_I2S1() APIs -definitions
      • +
    • Remove meaningless RCC_PLL_GetFreqDomain_SYS(), RCC_PLL_GetFreqDomain_ADC() and RCC_PLL_GetFreqDomain_I2S1() APIs definitions
  • LL TIM driver:
      -
    • Removed meaningless LL_TIM_ReArmBRK() and LL_TIM_ReArmBRK2() -functions
      • +
    • Removed meaningless LL_TIM_ReArmBRK() and LL_TIM_ReArmBRK2() functions
    • Fixed some typos in code comments
    • Improve LL_TIM_BDTR_Init() implementation consistency
    • Configure complementary channels only when supported
      • @@ -372,49 +392,41 @@

      LL Drivers updates

  • LL I2C driver:
      -
    • Update LL_I2C_HandleTranfer function to prevent undefined behavior -of volatile usage before updating the CR2 register.
      • +
    • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register.
  • LL SYSTEM driver:
      -
    • Correct LL_SYSCFG_IsActiveFlag_CLK_CTRL() and -LL_SYSCFG_IsActiveFlag_WWDG() implementation
      • +
    • Correct LL_SYSCFG_IsActiveFlag_CLK_CTRL() and LL_SYSCFG_IsActiveFlag_WWDG() implementation
  • LL UTILS driver:
      -
    • Remove IS_LL_UTILS_SYSCLK_DIV, IS_LL_UTILS_APB1_DIV, -IS_LL_UTILS_HSI_DIV, IS_LL_UTILS_HSIKER_DIV IS_LL_UTILS_HSE_BYPASS and -IS_LL_UTILS_HSE_FREQUENCY macros
      • +
    • Remove IS_LL_UTILS_SYSCLK_DIV, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_HSI_DIV, IS_LL_UTILS_HSIKER_DIV IS_LL_UTILS_HSE_BYPASS and IS_LL_UTILS_HSE_FREQUENCY macros
    • Remove useless LL_UTILS_ClkInitTypeDef structure
    • Correct LL_UTILS_PACKAGETYPE naming
      • -
    • Remove UTILS_HSE_FREQUENCY_MIN and UTILS_HSE_FREQUENCY_MAX -definitions
      • +
    • Remove UTILS_HSE_FREQUENCY_MIN and UTILS_HSE_FREQUENCY_MAX definitions

    • Note: HAL/LL Backward compatibility ensured by legacy defines.

    -

    Known Limitations

    +

    Known Limitations

    • None
    -

    Backward Compatibility

    +

    Backward Compatibility

    • Not applicable
    - - +
    -

    Main Changes

    +

    Main Changes

    • Maintenance Release of STM32CubeC0 Firmware Package

    HAL/LL Drivers updates

      -
    • HAL and LL drivers Maintenance Release for STM32C011xx / STM32C031xx -devices
      • +
    • HAL and LL drivers Maintenance Release for STM32C011xx / STM32C031xx devices

    – HAL Drivers updates

      @@ -438,21 +450,18 @@

      Main Changes

  • HAL UART driver
      -
    • Add (HAL_UART_RxEventTypeTypeDef RxEventType) to the -__UART_HandleTypeDef structure
      • +
    • Add (HAL_UART_RxEventTypeTypeDef RxEventType) to the __UART_HandleTypeDef structure
    • Add following defines:
      • HAL_UART_RXEVENT_TC (Transfer Complete event)
      • HAL_UART_RXEVENT_HT (Half Transfer event)
      • HAL_UART_RXEVENT_IDLE (IDLE event)
      • -
    • Add HAL_UARTEx_GetRxEventType() API to provide Rx Event type (to be -called within the user implementation of Rx Event Callback)
      • +
    • Add HAL_UARTEx_GetRxEventType() API to provide Rx Event type (to be called within the user implementation of Rx Event Callback)
  • HAL driver
      -
    • Update HAL_SYSCFG_SetPinBinding() to handle properly setting of a -pin biding (w/o overwriting existing pins binding settings).
      • +
    • Update HAL_SYSCFG_SetPinBinding() to handle properly setting of a pin biding (w/o overwriting existing pins binding settings).
    • Update HAL_SYSCFG_GetPinBinding() to get a pin biding setting.
    • @@ -462,73 +471,52 @@

    Main Changes

    • Add SYSTEM_LL_PINMUX_SOURCE following defines:
        -
      • LL_PINMUX_SO8_PIN1, LL_PINMUX_SO8_PIN4, LL_PINMUX_SO8_PIN5, -LL_PINMUX_SO8_PIN8, LL_PINMUX_WLCSP12_PINE2, LL_PINMUX_WLCSP12_PINF1 in -case of device STM32C011xx device
        • -
      • LL_PINMUX_WLCSP14_PINF2, LL_PINMUX_WLCSP14_PING3, -LL_PINMUX_WLCSP14_PINJ1, LL_PINMUX_WLCSP14_PINH2, -LL_PINMUX_WLCSP14_PING1, LL_PINMUX_WLCSP14_PINJ3 in case of device -STM32C031xx device
        • -
      • -
    • Update LL_SYSCFG_ConfigPinMux() and LL_SYSCFG_GetConfigPinMux() -functions
      • -
    • LL_SYSCFG_ConfigPinMux() API updated to handle properly setting of a -pin binding (w/o overwriting existing pins biding settings).
      • -
    • LL_SYSCFG_GetConfigPinMux() API updated to get a pin biding -setting.
      • +
    • LL_PINMUX_SO8_PIN1, LL_PINMUX_SO8_PIN4, LL_PINMUX_SO8_PIN5, LL_PINMUX_SO8_PIN8, LL_PINMUX_WLCSP12_PINE2, LL_PINMUX_WLCSP12_PINF1 in case of device STM32C011xx device
      • +
    • LL_PINMUX_WLCSP14_PINF2, LL_PINMUX_WLCSP14_PING3, LL_PINMUX_WLCSP14_PINJ1, LL_PINMUX_WLCSP14_PINH2, LL_PINMUX_WLCSP14_PING1, LL_PINMUX_WLCSP14_PINJ3 in case of device STM32C031xx device
      • +
    +
  • Update LL_SYSCFG_ConfigPinMux() and LL_SYSCFG_GetConfigPinMux() functions
    • +
  • LL_SYSCFG_ConfigPinMux() API updated to handle properly setting of a pin binding (w/o overwriting existing pins biding settings).
    • +
  • LL_SYSCFG_GetConfigPinMux() API updated to get a pin biding setting.
    • -

    Known Limitations

    +

    Known Limitations

    N/A

    -

    Backward Compatibility

    +

    Backward Compatibility

      -
    • HAL_SYSCFG_GetPinBinding() and LL_SYSCFG_GetConfigPinMux() are -updated.
      • +
    • HAL_SYSCFG_GetPinBinding() and LL_SYSCFG_GetConfigPinMux() are updated.
    - - +
    -

    Main Changes

    +

    Main Changes

    • Patch Release of STM32CubeC0 Firmware Package

      • -

    • Update ADC HAL driver with proper internal sensor calibration -implementation:

      +
    • Update ADC HAL driver with proper internal sensor calibration implementation:
        -
      • Helper macro “__LL_ADC_CALC_TEMPERATURE()” is not available and -macro “__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()” must be used.
        • +
      • Helper macro "__LL_ADC_CALC_TEMPERATURE()" is not available and macro "__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()" must be used.

    • Update RCC LL driver by adding missing AHB Prescaler.

    -

    Known Limitations

    +

    Known Limitations

    N/A

    - - +
    -

    Main Changes

    -

    First official release of HAL and LL drivers for STM32C031xx / -STM32C011xx devices

    -

    Known Limitations

    +

    Main Changes

    +

    First official release of HAL and LL drivers for STM32C031xx / STM32C011xx devices

    +

    Known Limitations

    N/A

    -
    +
    -

    For complete documentation on STM32 Microcontrollers , visit: -www.st.com/stm32

    -This release note uses up to date web standards and, for this reason, -should not be opened with Internet Explorer but preferably with popular -browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft -Edge. +

    For complete documentation on STM32 Microcontrollers , visit: www.st.com/stm32

    +This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.
    diff --git a/system/Drivers/STM32C0xx_HAL_Driver/SW_Security_Level.md b/system/Drivers/STM32C0xx_HAL_Driver/SW_Security_Level.md new file mode 100644 index 0000000000..08b5a06b5e --- /dev/null +++ b/system/Drivers/STM32C0xx_HAL_Driver/SW_Security_Level.md @@ -0,0 +1,47 @@ + + +## Copyright (c) 2026 STMicroelectronics. +## All rights reserved +
    +
    + +## SW Security Classification + +[STM32Trust software security policies](https://wiki.st.com/stm32mcu/wiki/Security:STM32Trust_software_security_policies) define four levels of SW Security classification, each level defines a set of security policies for the applicable SW. + +| SW | SW Security Level +|:--------- |:-------| +| **STM32C0xx HAL Driver** | Medium| + + +
    + +## IMPORTANT SECURITY NOTICE + +The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that: + +- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified. + +- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product. + +- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies. + +- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application. + +- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. + +AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. + +
    + +## IMPORTANT NOTICE - READ CAREFULLY + +STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. + +Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. +No license, express or implied, to any intellectual property right is granted by ST herein. +Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. +ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. +Information in this document supersedes and replaces information previously supplied in any prior versions of this document. + +Copyright (c) 2026 STMicroelectronics - All rights reserved \ No newline at end of file diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c index 8acd76d82b..7e3076a9e2 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c @@ -55,10 +55,10 @@ /** * @brief STM32C0xx HAL Driver version number */ -#define __STM32C0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32C0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32C0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32C0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32C0xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32C0xx_HAL_VERSION_SUB1 (0x04UL) /*!< [23:16] sub1 version */ +#define __STM32C0xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */ +#define __STM32C0xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32C0xx_HAL_VERSION ((__STM32C0xx_HAL_VERSION_MAIN << 24U)\ |(__STM32C0xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32C0xx_HAL_VERSION_SUB2 << 8U )\ @@ -332,17 +332,25 @@ uint32_t HAL_GetTickPrio(void) HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); - if (status == HAL_OK) + if (status != HAL_OK) { - uwTickFreq = Freq; + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; } } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c index 5f67417d20..adcec2529c 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c @@ -528,10 +528,6 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; - /* Process Unlocked/locked */ - __HAL_UNLOCK(hdma); - __HAL_LOCK(hdma); - if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c index 06d799e002..12e2a263fb 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c @@ -580,17 +580,19 @@ uint32_t HAL_FLASH_GetError(void) HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { uint32_t error; + uint32_t tickstart = HAL_GetTick(); /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; - /* Wait if any operation is ongoing */ while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0x00U) { - if (HAL_GetTick() >= timeout) + if (Timeout != HAL_MAX_DELAY) { - return HAL_TIMEOUT; + if(((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } } } @@ -609,13 +611,15 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } /* Wait for control register to be written */ - timeout = HAL_GetTick() + Timeout; while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY) != 0x00U) { - if (HAL_GetTick() >= timeout) + if (Timeout != HAL_MAX_DELAY) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) >= Timeout) + { + return HAL_TIMEOUT; + } } } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c index 0739a0dde7..595c8195c1 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c @@ -429,7 +429,7 @@ uint32_t HAL_FLASHEx_FlashEmptyCheck(void) /** * @brief Force Empty check value. * @note Allows to modify program empty check value in order to force this - * infrmation in Flash Interface, for all next reset that do not launch + * information in Flash Interface, for all next reset that do not launch * Option Byte Loader. * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check * @retval None diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_hcd.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_hcd.c index 8c392dbeb9..d9c47c1365 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_hcd.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_hcd.c @@ -46,6 +46,9 @@ (#)Enable HCD transmission and reception: (##) HAL_HCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -336,7 +339,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* This is a dual EP0 PMA allocation */ - hhcd->ep0_PmaAllocState |= (0x1U << 12); + hhcd->ep0_PmaAllocState |= (0x1UL << 12); /* PMA Dynamic Allocation for EP0 OUT direction */ hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; @@ -1012,8 +1015,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); if (hhcd->State == HAL_HCD_STATE_READY) { @@ -1083,8 +1084,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -1108,9 +1107,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - /* Setup Legacy weak Callbacks */ if (hhcd->State == HAL_HCD_STATE_READY) { @@ -1183,8 +1179,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); return status; } @@ -1208,9 +1202,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = pCallback; @@ -1224,9 +1215,6 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } @@ -1241,9 +1229,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hhcd); - if (hhcd->State == HAL_HCD_STATE_READY) { hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ @@ -1257,9 +1242,6 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; } #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ @@ -1552,6 +1534,24 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu return HAL_OK; } +/** + * @brief Activate a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Activate(hhcd->Instance, (uint8_t)ch_num, hhcd->hc[ch_num].ch_dir); + __HAL_UNLOCK(hhcd); + + return status; +} + #if (USE_USB_DOUBLE_BUFFER == 1U) /** * @brief Handle Host Channel OUT Double Buffer Bulk requests. @@ -2209,39 +2209,11 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - uint32_t FnrReg = hhcd->Instance->FNR; uint32_t IstrReg = hhcd->Instance->ISTR; - /* SE0 detected USB Disconnected state */ - if ((FnrReg & (USB_FNR_RXDP | USB_FNR_RXDM)) == 0U) + /* SE0 detected USB Disconnected state */ + if ((IstrReg & USB_ISTR_DCON_STAT) == USB_ISTR_DCON_STAT) { - /* Host Port State */ - hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - - /* Clear all allocated virtual channel */ - HAL_HCD_ClearPhyChannel(hhcd); - - /* Reset the PMA current pointer */ - (void)HAL_HCD_PMAReset(hhcd); - - /* Reset Ep0 Pma allocation state */ - hhcd->ep0_PmaAllocState = 0U; - - /* Disconnection Callback */ -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); -#else - HAL_HCD_Disconnect_Callback(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - return; - } - - if ((hhcd->HostState == HCD_HCD_STATE_DISCONNECTED) != 0U) - { - /* J-state or K-state detected & LastState=Disconnected */ - if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) - { hhcd->HostState = HCD_HCD_STATE_CONNECTED; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) @@ -2249,32 +2221,27 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) #else HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } } else { - /* J-state or K-state detected & lastState=Connected: a Missed disconnection is detected */ - if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) - { - /* Host Port State */ - hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - /* clear all allocated virtual channel */ - HAL_HCD_ClearPhyChannel(hhcd); + /* clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); - /* Reset the PMA current pointer */ - (void)HAL_HCD_PMAReset(hhcd); + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); - /* reset Ep0 PMA allocation state */ - hhcd->ep0_PmaAllocState = 0U; + /* reset Ep0 PMA allocation state */ + hhcd->ep0_PmaAllocState = 0U; - /* Disconnection Callback */ + /* Disconnection Callback */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); + hhcd->DisconnectCallback(hhcd); #else - HAL_HCD_Disconnect_Callback(hhcd); + HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } } } @@ -2553,7 +2520,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) while ((j <= 31U) && (FreeBlocks != NbrReqBlocks)) { /* check if block j is free */ - if ((Entry & ((uint32_t)1U << j)) == 0U) + if ((Entry & ((uint32_t)1UL << j)) == 0U) { if (FreeBlocks == 0U) { @@ -2564,7 +2531,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) j++; /* Parse Column PMALockTable */ - while ((j <= 31U) && ((Entry & ((uint32_t)1U << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) + while ((j <= 31U) && ((Entry & ((uint32_t)1UL << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) { FreeBlocks++; j++; @@ -2572,7 +2539,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) /* Free contiguous Blocks not found */ if (((FreeBlocks < NbrReqBlocks) && (j < 31U)) || - ((j == 31U) && ((Entry & ((uint32_t)1U << j)) != 0U))) + ((j == 31U) && ((Entry & ((uint32_t)1UL << j)) != 0U))) { FreeBlocks = 0U; } @@ -2590,7 +2557,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) { for (uint8_t j = ColIndex; j <= 31U; j++) { - hhcd->PMALookupTable[i] |= ((uint32_t)1U << j); + hhcd->PMALookupTable[i] |= ((uint32_t)1UL << j); if (--FreeBlocks == 0U) { break; @@ -2649,7 +2616,7 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, { hhcd->ep0_PmaAllocState &= 0xFFF0U; hhcd->ep0_PmaAllocState |= ch_num; - hhcd->ep0_PmaAllocState |= (1U << 8); + hhcd->ep0_PmaAllocState |= (1UL << 8); } /* Configure the PMA */ @@ -2782,7 +2749,7 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd) /* Allocate a Space for buffer descriptor table depending on the Host channel number */ for (uint8_t i = 0U; i < hhcd->Init.Host_channels; i++) { - hhcd->PMALookupTable[0] |= ((uint32_t)1U << i); + hhcd->PMALookupTable[0] |= ((uint32_t)1UL << i); } return HAL_OK; @@ -2844,12 +2811,12 @@ static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_ for (uint8_t j = ColIndex; j <= 31U; j++) { /* Check if the block is not already reserved or it was already closed */ - if ((hhcd->PMALookupTable[i] & ((uint32_t)1U << j)) == 0U) + if ((hhcd->PMALookupTable[i] & ((uint32_t)1UL << j)) == 0U) { return HAL_ERROR; } /* Free the reserved block by resetting the corresponding bit */ - hhcd->PMALookupTable[i] &= ~(1U << j); + hhcd->PMALookupTable[i] &= ~(1UL << j); if (--block_nbr == 0U) { diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2s.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2s.c index b5d576a962..8f79daaf12 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2s.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_i2s.c @@ -1604,7 +1604,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval HAL state */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) { return hi2s->State; } @@ -1615,7 +1615,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c index 4ddfc4347f..bdcddfeb80 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd.c @@ -49,6 +49,9 @@ (#)Enable PCD transmission and reception: (##) HAL_PCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -311,8 +314,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); if (hpcd->State == HAL_PCD_STATE_READY) { @@ -390,8 +391,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -416,9 +415,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - /* Setup Legacy weak Callbacks */ if (hpcd->State == HAL_PCD_STATE_READY) { @@ -499,8 +495,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); return status; } @@ -524,9 +518,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = pCallback; @@ -540,9 +531,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -556,9 +544,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ @@ -572,9 +557,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -598,9 +580,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = pCallback; @@ -614,9 +593,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -630,9 +606,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ @@ -646,9 +619,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -672,9 +642,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = pCallback; @@ -688,9 +655,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -705,9 +669,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ @@ -721,9 +682,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -747,9 +705,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = pCallback; @@ -763,9 +718,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -780,9 +732,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ @@ -796,9 +745,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -821,9 +767,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->BCDCallback = pCallback; @@ -837,9 +780,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -853,9 +793,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ @@ -869,9 +806,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -894,9 +828,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->LPMCallback = pCallback; @@ -910,9 +841,6 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } @@ -926,9 +854,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpcd); - if (hpcd->State == HAL_PCD_STATE_READY) { hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ @@ -942,9 +867,6 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; } #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ @@ -1125,6 +1047,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->SOFCallback(hpcd); #else @@ -1718,6 +1643,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) count = 0U; #endif /* USE_USB_DOUBLE_BUFFER */ + /* store current frame number */ + hpcd->FrameNumber = USB_GetCurrentFrame(hpcd->Instance); + /* stay in loop while pending interrupts */ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { @@ -1726,6 +1654,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_IDN); + if (epindex >= 8U) + { + return HAL_ERROR; + } + if (epindex == 0U) { /* Decode and service control endpoint interrupt */ @@ -1770,6 +1703,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); @@ -1790,26 +1735,27 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + if (ep->xfer_count == 0U) + { + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ - ep->xfer_buff += ep->xfer_count; + ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet */ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1875,7 +1821,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - ep->xfer_buff += count; if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { @@ -1888,6 +1833,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + ep->xfer_buff += count; (void)USB_EPStartXfer(hpcd->Instance, ep); } } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd_ex.c index f15a393d98..69077e4e46 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd_ex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pcd_ex.c @@ -82,7 +82,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { PCD_EPTypeDef *ep; - /* initialize ep structure*/ + /* Initialize ep structure */ if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; @@ -97,6 +97,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Single Buffer */ ep->doublebuffer = 0U; + /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } @@ -105,6 +106,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; + /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); @@ -124,13 +126,11 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) USB_DRD_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 1U; - /* Enable BCD feature */ - USBx->BCDR |= USB_BCDR_BCDEN; - - /* Enable DCD : Data Contact Detect */ USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR &= ~(USB_BCDR_SDEN); - USBx->BCDR |= USB_BCDR_DCDEN; + + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; return HAL_OK; } @@ -162,21 +162,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) uint32_t tickstart = HAL_GetTick(); /* Wait for Min DCD Timeout */ - HAL_Delay(300U); + HAL_Delay(350U); - /* Data Pin Contact ? Check Detect flag */ - if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->BCDR &= ~(USB_BCDR_DCDEN); - HAL_Delay(50U); USBx->BCDR |= (USB_BCDR_PDEN); HAL_Delay(50U); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c index 247a01aa44..83d398ab4d 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c @@ -820,10 +820,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStru /** * @brief Select the clock source to output on MCOx pin. - * @note PA8 for MCO1 and PB2 for MCO2 should be configured in alternate function mode. + * @note The selected MCOx pin should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pins. - * @arg @ref RCC_MCO2 Clock source to output on MCO2 pins. + * @arg @ref RCC_MCO1_PA8 Clock source to output on MCO1 pin(PA8) + * @arg @ref RCC_MCO1_PA9 Clock source to output on MCO1 pin(PA9) + * @arg @ref RCC_MCO1_PF2 Clock source to output on MCO1 pin(PF2) + * @arg @ref RCC_MCO2_PA8 Clock source to output on MCO2 pin(PA8) + * @arg @ref RCC_MCO2_PA10 Clock source to output on MCO2 pin(PA10) + * @arg @ref RCC_MCO2_PA14 Clock source to output on MCO2 pin(PA14) + * @arg @ref RCC_MCO2_PA15 Clock source to output on MCO2 pin(PA15)(*) + * @arg @ref RCC_MCO2_PB2 Clock source to output on MCO2 pin(PB2)(*) * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO1 output disabled, no clock on MCO1 diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard.c index 1c072c2693..0612beab17 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_smartcard.c @@ -2390,14 +2390,6 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); - /*-------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = hsmartcard->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; - tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure * - one-bit sampling method versus three samples' majority rule @@ -2419,6 +2411,14 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c index 691f1d9b39..84b8173757 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -69,9 +70,8 @@ (##) HAL_SPI_Init() [..] Data buffer address alignment restriction: - (#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer. - But there is no support for unaligned accesses on the Cortex-M0 processor. - So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for: + (#) There is no support for unaligned accesses on the Cortex-M0 processor. + If the user wants to transfer in 16Bit data mode, it shall ensure that 16-bit aligned address is used for: (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT() (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT() (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA() @@ -199,7 +199,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -822,9 +823,9 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -832,7 +833,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData uint32_t tickstart; uint16_t initial_TxXferCount; - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* in this case, 16-bit access is performed on Data So, check Data is 16-bit aligned address */ @@ -932,38 +933,18 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - if (hspi->TxXferCount > 1U) - { - /* write on the data register in packing mode */ - hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr ++; - hspi->TxXferCount--; - } + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; } while (hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - if (hspi->TxXferCount > 1U) - { - /* write on the data register in packing mode */ - hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; } else { @@ -1015,10 +996,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -1029,7 +1013,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 #endif /* USE_SPI_CRC */ uint32_t tickstart; - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* in this case, 16-bit access is performed on Data So, check Data is 16-bit aligned address */ @@ -1041,6 +1025,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_BUSY; } + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1051,11 +1040,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1264,17 +1248,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; - uint16_t initial_RxXferCount; uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; @@ -1289,7 +1272,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* in this case, 16-bit access is performed on Data So, check Data is 16-bit aligned address */ @@ -1307,14 +1290,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; initial_TxXferCount = Size; - initial_RxXferCount = Size; #if (USE_SPI_CRC != 0U) spi_cr1 = READ_REG(hspi->Instance->CR1); spi_cr2 = READ_REG(hspi->Instance->CR2); #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; } @@ -1355,7 +1338,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -1443,49 +1426,31 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - if (hspi->TxXferCount > 1U) - { - hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; #if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } -#endif /* USE_SPI_CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - if (hspi->TxXferCount > 1U) - { - hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; @@ -1506,23 +1471,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) { - if (hspi->RxXferCount > 1U) - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2U; - if (hspi->RxXferCount <= 1U) - { - /* Set RX Fifo threshold before to switch on 8 bit data size */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - } - else - { - (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; - hspi->pRxBuffPtr++; - hspi->RxXferCount--; - } + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; } @@ -1621,14 +1572,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* in this case, 16-bit access is performed on Data So, check Data is 16-bit aligned address */ @@ -1710,13 +1661,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* in this case, 16-bit access is performed on Data So, check Data is 16-bit aligned address */ @@ -1729,6 +1680,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_BUSY; } + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1737,11 +1693,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1820,9 +1771,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, @@ -1831,7 +1782,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U))) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* in this case, 16-bit access is performed on Data So, check Data is 16-bit aligned address */ @@ -1847,7 +1798,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; } @@ -1936,8 +1888,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) @@ -2056,9 +2008,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -2071,6 +2023,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u return HAL_BUSY; } + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -2082,11 +2039,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -2195,10 +2147,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, @@ -2219,7 +2171,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { return HAL_BUSY; } @@ -2466,7 +2419,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2499,7 +2453,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2754,9 +2709,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -3085,7 +3042,7 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3142,7 +3099,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3259,7 +3216,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3297,7 +3254,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3359,7 +3317,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3377,7 +3335,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3395,7 +3353,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3413,7 +3371,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3436,7 +3394,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3458,7 +3416,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3474,7 +3432,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3524,7 +3483,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3541,7 +3500,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3592,8 +3552,10 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Receive data in packing mode */ if (hspi->RxXferCount > 1U) { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); - hspi->pRxBuffPtr += sizeof(uint16_t); + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; hspi->RxXferCount -= 2U; if (hspi->RxXferCount == 1U) { @@ -3674,20 +3636,10 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - /* Transmit data in packing Bit mode */ - if (hspi->TxXferCount >= 2U) - { - hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } /* Transmit data in 8 Bit mode */ - else - { - *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) @@ -4036,7 +3988,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4118,7 +4073,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4414,7 +4372,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4457,7 +4416,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4486,7 +4446,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c index 6314992d74..559d19885b 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c @@ -6976,6 +6976,9 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + /* Ensure that the update event is generated before writing back CR1 register with URS = 0 */ + __DSB(); + TIMx->CR1 = tmpcr1; } @@ -7019,12 +7022,13 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 1N: Reset the CC1NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC1NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7095,12 +7099,13 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 2N: Reset the CC2NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC2NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7170,12 +7175,13 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 3N: Reset the CC3NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC3NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7522,9 +7528,18 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7568,9 +7583,18 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7612,9 +7636,18 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7651,9 +7684,18 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7695,9 +7737,18 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 3: Reset the CC3E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; + /* Disable the Channel 3N: Reset the CC3NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + TIMx->CCER &= ~TIM_CCER_CC3NE; + } + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7743,9 +7794,13 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 4: Reset the CC4E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7832,10 +7887,10 @@ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param ChannelState specifies the TIM Channel CCxE bit new state. diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c index a6efe80b5a..f45f4f6e2a 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c @@ -2613,9 +2613,9 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) @@ -2774,9 +2774,9 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_tim_template.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_tim_template.c index 5b4ffc9f8b..91c2030913 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_timebase_tim_template.c @@ -53,6 +53,9 @@ extern TIM_HandleTypeDef TimHandle; TIM_HandleTypeDef TimHandle; /* Private function prototypes -----------------------------------------------*/ void TIM3_IRQHandler(void); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Private functions ---------------------------------------------------------*/ /** @@ -116,6 +119,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&TimHandle); } @@ -154,8 +161,15 @@ void HAL_ResumeTick(void) * @param htim TIM handle * @retval None */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#else void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + HAL_IncTick(); } diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c index 4bfdfcc715..238e525c00 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c @@ -642,8 +642,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0U; huart->Instance->CR2 = 0x0U; huart->Instance->CR3 = 0x0U; @@ -1188,7 +1186,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1300,7 +1306,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1802,10 +1816,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1874,9 +1884,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -1941,9 +1948,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -2071,10 +2075,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -2155,8 +2155,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2177,9 +2175,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2254,9 +2249,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2283,9 +2275,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -3837,7 +3826,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3845,7 +3833,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3869,7 +3856,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -3903,10 +3889,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3958,10 +3940,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3999,8 +3977,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -4032,8 +4008,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rtc.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rtc.c index 0b2a5e63f2..03fa844001 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rtc.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_rtc.c @@ -148,8 +148,9 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) { /* Reset TR, DR and CR registers */ WRITE_REG(RTCx->TR, 0U); - WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + WRITE_REG(RTCx->CR, 0U); WRITE_REG(RTCx->ALRMAR, 0U); WRITE_REG(RTCx->SHIFTR, 0U); WRITE_REG(RTCx->CALR, 0U); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_spi.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_spi.c index cee461d012..9c7f8827ac 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_spi.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_spi.c @@ -167,8 +167,9 @@ ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -370,7 +371,7 @@ ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) * - SUCCESS: SPI registers are Initialized * - ERROR: SPI registers are not Initialized */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx,const LL_I2S_InitTypeDef *I2S_InitStruct) { uint32_t i2sdiv = 2U; uint32_t i2sodd = 0U; diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c index 7cf93e996a..a8b632a5a5 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_tim.c @@ -31,7 +31,13 @@ * @{ */ -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) +#if defined (TIM1) \ + || defined (TIM2) \ + || defined (TIM3) \ + || defined (TIM14) \ + || defined (TIM15) \ + || defined (TIM16) \ + || defined (TIM17) /** @addtogroup TIM_LL * @{ @@ -578,8 +584,6 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note Channel 2 is configured in output PWM 2 mode. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. * @note OC2REF is selected as trigger output on TRGO. - * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used - * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor * interface configuration data structure) @@ -639,7 +643,7 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_In /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + tmpccer |= (uint32_t)(TIM_CCER_CC1E); /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); diff --git a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c index 50c4fe36d0..9f20518234 100644 --- a/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c +++ b/system/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_ll_usb.c @@ -33,6 +33,9 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** @@ -55,6 +58,7 @@ /* Private functions ---------------------------------------------------------*/ static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); +#if defined (HAL_HCD_MODULE_ENABLED) #if (USE_USB_DOUBLE_BUFFER == 1U) static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc, @@ -65,6 +69,7 @@ static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc, uint32_t len); #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** * @brief Reset the USB Core (needed after USB clock settings change) @@ -970,6 +975,16 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABu } } +/** + * @brief Return Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) +{ + return (uint32_t)(USBx->FNR & 0x7FFU); +} + /*------------------------------------------------------------------------*/ /* HOST API */ @@ -1049,43 +1064,7 @@ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx) } } -/** - * @brief Return Host Current Frame number - * @param USBx Selected device - * @retval current frame number - */ -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) -{ - return USBx->FNR & 0x7FFU; -} - -/** - * @brief Set the channel Kind (Single/double buffer mode) - * @param USBx Selected device - * @param phy_ch_num Selected device - * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, - uint8_t phy_ch_num, uint8_t db_state) -{ - uint32_t tmp; - - if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) - { - tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; - } - else - { - tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; - } - - /* Set the device speed in case using HUB FS with device LS */ - USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); - - return HAL_OK; -} - +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel * @param USBx Selected device @@ -1153,7 +1132,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, USB_CHEP_KIND | USB_CHEP_ERRTX | USB_CHEP_ERRRX | - (0xFU << 27)); + (0xFUL << 27)); /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | @@ -1174,6 +1153,33 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, return ret; } +/** + * @brief Set the channel Kind (Single/double buffer mode) + * @param USBx Selected device + * @param phy_ch_num Selected device + * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, + uint8_t phy_ch_num, uint8_t db_state) +{ + uint32_t tmp; + + if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) + { + tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; + } + else + { + tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; + } + + /* Set the device speed in case using HUB FS with device LS */ + USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); + + return HAL_OK; +} + /** * @brief Start a transfer over a host channel * @param USBx Selected device @@ -1414,14 +1420,13 @@ static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, /** * @brief Halt a host channel in * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 + * @param phy_ch_num Host Channel number * @retval HAL state */ -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num) { /* Set disable to Channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS); + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_DIS); return HAL_OK; } @@ -1430,17 +1435,40 @@ HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) /** * @brief Halt a host channel out * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 + * @param phy_ch_num Host Channel number * @retval HAL state */ -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num) { /* Set disable to Channel */ - USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS); + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_DIS); + + return HAL_OK; +} + +/** + * @brief Activate a host channel + * @param USBx Selected device + * @param phy_ch_num Host Channel number + * @param ch_dir Host Channel direction + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir) +{ + if (ch_dir == CH_IN_DIR) + { + /* Enable TX host Channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_VALID); + } + else + { + /* Enable RX host Channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); + } return HAL_OK; } +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** * @brief Stop Host Core diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index b2b35402c5..05cd9b2113 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -1,6 +1,6 @@ # STM32YYxx HAL Drivers version: - * STM32C0: 1.4.0 + * STM32C0: 1.4.1 * STM32C5: 2.1.0 * STM32F0: 1.7.8 * STM32F1: 1.1.10 From d59113f3909222110c651167e8205b932de156aa Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 20 Jul 2026 11:08:44 +0200 Subject: [PATCH 2/2] system(c0): update STM32C0xx CMSIS Drivers to v1.4.1 Included in STM32CubeC0 FW v1.4.1 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32C0xx/Include/stm32c011xx.h | 4 +- .../Device/ST/STM32C0xx/Include/stm32c031xx.h | 4 +- .../Device/ST/STM32C0xx/Include/stm32c051xx.h | 4 +- .../Device/ST/STM32C0xx/Include/stm32c071xx.h | 4 +- .../Device/ST/STM32C0xx/Include/stm32c091xx.h | 6 +- .../Device/ST/STM32C0xx/Include/stm32c092xx.h | 6 +- .../Device/ST/STM32C0xx/Include/stm32c0xx.h | 6 +- .../CMSIS/Device/ST/STM32C0xx/LICENSE.md | 2 +- .../CMSIS/Device/ST/STM32C0xx/README.md | 4 +- .../Device/ST/STM32C0xx/Release_Notes.html | 172 ++++++++---------- .../Device/ST/STM32C0xx/Release_Notes.md | 134 ++++++++++++++ .../Templates/gcc/startup_stm32c091xx.s | 68 +++---- .../Templates/gcc/startup_stm32c092xx.s | 68 +++---- .../Source/Templates/system_stm32c0xx.c | 4 + .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 15 files changed, 301 insertions(+), 187 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.md diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h index c45c968353..a9f2c1c770 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h @@ -4239,10 +4239,8 @@ typedef struct #define RCC_CSR1_LSEBYP_Msk (0x1UL << RCC_CSR1_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_CSR1_LSEBYP RCC_CSR1_LSEBYP_Msk #define RCC_CSR1_LSEDRV_Pos (3U) -#define RCC_CSR1_LSEDRV_Msk (0x3UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_CSR1_LSEDRV_Msk (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ #define RCC_CSR1_LSEDRV RCC_CSR1_LSEDRV_Msk -#define RCC_CSR1_LSEDRV_0 (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ -#define RCC_CSR1_LSEDRV_1 (0x2UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000010 */ #define RCC_CSR1_LSECSSON_Pos (5U) #define RCC_CSR1_LSECSSON_Msk (0x1UL << RCC_CSR1_LSECSSON_Pos) /*!< 0x00000020 */ #define RCC_CSR1_LSECSSON RCC_CSR1_LSECSSON_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h index 5cc3591609..cc3439ba8a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h @@ -4402,10 +4402,8 @@ typedef struct #define RCC_CSR1_LSEBYP_Msk (0x1UL << RCC_CSR1_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_CSR1_LSEBYP RCC_CSR1_LSEBYP_Msk #define RCC_CSR1_LSEDRV_Pos (3U) -#define RCC_CSR1_LSEDRV_Msk (0x3UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_CSR1_LSEDRV_Msk (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ #define RCC_CSR1_LSEDRV RCC_CSR1_LSEDRV_Msk -#define RCC_CSR1_LSEDRV_0 (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ -#define RCC_CSR1_LSEDRV_1 (0x2UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000010 */ #define RCC_CSR1_LSECSSON_Pos (5U) #define RCC_CSR1_LSECSSON_Msk (0x1UL << RCC_CSR1_LSECSSON_Pos) /*!< 0x00000020 */ #define RCC_CSR1_LSECSSON RCC_CSR1_LSECSSON_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h index fc8e34a0f9..ceab6091ac 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h @@ -4523,10 +4523,8 @@ typedef struct #define RCC_CSR1_LSEBYP_Msk (0x1UL << RCC_CSR1_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_CSR1_LSEBYP RCC_CSR1_LSEBYP_Msk #define RCC_CSR1_LSEDRV_Pos (3U) -#define RCC_CSR1_LSEDRV_Msk (0x3UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_CSR1_LSEDRV_Msk (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ #define RCC_CSR1_LSEDRV RCC_CSR1_LSEDRV_Msk -#define RCC_CSR1_LSEDRV_0 (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ -#define RCC_CSR1_LSEDRV_1 (0x2UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000010 */ #define RCC_CSR1_LSECSSON_Pos (5U) #define RCC_CSR1_LSECSSON_Msk (0x1UL << RCC_CSR1_LSECSSON_Pos) /*!< 0x00000020 */ #define RCC_CSR1_LSECSSON RCC_CSR1_LSECSSON_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c071xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c071xx.h index d80e46b859..064e3f3c03 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c071xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c071xx.h @@ -4895,10 +4895,8 @@ typedef struct #define RCC_CSR1_LSEBYP_Msk (0x1UL << RCC_CSR1_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_CSR1_LSEBYP RCC_CSR1_LSEBYP_Msk #define RCC_CSR1_LSEDRV_Pos (3U) -#define RCC_CSR1_LSEDRV_Msk (0x3UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_CSR1_LSEDRV_Msk (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ #define RCC_CSR1_LSEDRV RCC_CSR1_LSEDRV_Msk -#define RCC_CSR1_LSEDRV_0 (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ -#define RCC_CSR1_LSEDRV_1 (0x2UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000010 */ #define RCC_CSR1_LSECSSON_Pos (5U) #define RCC_CSR1_LSECSSON_Msk (0x1UL << RCC_CSR1_LSECSSON_Pos) /*!< 0x00000020 */ #define RCC_CSR1_LSECSSON RCC_CSR1_LSECSSON_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c091xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c091xx.h index f3a7a0b513..09a147e9d1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c091xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c091xx.h @@ -103,6 +103,8 @@ typedef enum USART3_4_IRQn = 29, /*!< USART3/4 global interrupt(combined with EXTI 28) */ } IRQn_Type; +/* Legacy define */ +#define DMAMUX1_DMA1_CH4_5_IRQHandler DMAMUX1_DMA1_CH4_5_6_7_IRQHandler /** * @} */ @@ -4725,10 +4727,8 @@ typedef struct #define RCC_CSR1_LSEBYP_Msk (0x1UL << RCC_CSR1_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_CSR1_LSEBYP RCC_CSR1_LSEBYP_Msk #define RCC_CSR1_LSEDRV_Pos (3U) -#define RCC_CSR1_LSEDRV_Msk (0x3UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_CSR1_LSEDRV_Msk (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ #define RCC_CSR1_LSEDRV RCC_CSR1_LSEDRV_Msk -#define RCC_CSR1_LSEDRV_0 (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ -#define RCC_CSR1_LSEDRV_1 (0x2UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000010 */ #define RCC_CSR1_LSECSSON_Pos (5U) #define RCC_CSR1_LSECSSON_Msk (0x1UL << RCC_CSR1_LSECSSON_Pos) /*!< 0x00000020 */ #define RCC_CSR1_LSECSSON RCC_CSR1_LSECSSON_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c092xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c092xx.h index 28869513c2..23c549b5e9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c092xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c092xx.h @@ -105,6 +105,8 @@ typedef enum FDCAN1_IT1_IRQn = 31, /*!< FDCAN1 global Interrupt 1 */ } IRQn_Type; +/* Legacy define */ +#define DMAMUX1_DMA1_CH4_5_IRQHandler DMAMUX1_DMA1_CH4_5_6_7_IRQHandler /** * @} */ @@ -5389,10 +5391,8 @@ typedef struct #define RCC_CSR1_LSEBYP_Msk (0x1UL << RCC_CSR1_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_CSR1_LSEBYP RCC_CSR1_LSEBYP_Msk #define RCC_CSR1_LSEDRV_Pos (3U) -#define RCC_CSR1_LSEDRV_Msk (0x3UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_CSR1_LSEDRV_Msk (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ #define RCC_CSR1_LSEDRV RCC_CSR1_LSEDRV_Msk -#define RCC_CSR1_LSEDRV_0 (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ -#define RCC_CSR1_LSEDRV_1 (0x2UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000010 */ #define RCC_CSR1_LSECSSON_Pos (5U) #define RCC_CSR1_LSECSSON_Msk (0x1UL << RCC_CSR1_LSECSSON_Pos) /*!< 0x00000020 */ #define RCC_CSR1_LSECSSON RCC_CSR1_LSECSSON_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h index de1b2988ed..6cf8e36e6a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h @@ -80,11 +80,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.0.0 + * @brief CMSIS Device version number V1.4.1 */ #define __STM32C0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32C0_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32C0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32C0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32C0_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32C0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32C0_CMSIS_VERSION ((__STM32C0_CMSIS_VERSION_MAIN << 24)\ |(__STM32C0_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/LICENSE.md b/system/Drivers/CMSIS/Device/ST/STM32C0xx/LICENSE.md index 22ed1674c4..2e8e072e86 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/LICENSE.md +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/LICENSE.md @@ -198,4 +198,4 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. + limitations under the License. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32C0xx/README.md index 9e8bb79c8c..d54c2fbd56 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/README.md @@ -1,6 +1,6 @@ # STM32CubeC0 CMSIS Device MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_c0.svg?color=brightgreen) +![tag](https://img.shields.io/badge/tag-v1.4.1-brightgreen.svg) ## Overview @@ -33,4 +33,4 @@ The full **STM32CubeC0** MCU package is available [here](https://github.com/STMi ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.html index 9890d3f442..80ecc5a288 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.html @@ -5,172 +5,156 @@ Release Notes for STM32C0xx CMSIS - - +
    -

    Release Notes for - STM32C0xx CMSIS

    +

    Release Notes for  STM32C0xx CMSIS

    Copyright © 2022 STMicroelectronics

    - +
    -
    -

    Update History

    +
    +

    Update History

    - - +

    Main Changes

      -
    • Official release of STM32C0xx CMSIS drivers to support -STM32C051xx and STM32C091/92xx -devices
    • General updates to fix known defects and enhance implementation
      • -
    • Align version of bit and registers definition with the STM32C0 -reference manual

    Contents

      +
    • Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.
      • +
    • Fix RCC_CSR1_LSEDRV_Msk definition to match actual field width
      • +
    • Fix DMAMUX1/DMA1 shared interrupt handler name
      • +
    • Add IAR linker configuration file for STM32C071x8
      • +
    +

    Supported Devices

    +
      +
    • STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx and STM32C091/92xx devices
      • +
    +
    +
    +
    + +
    +

    Main Changes

    +
      +
    • No CMSIS-related fixes were included in this release.
      • +
    +
    +
    +
    + +
    +

    Main Changes

    +
      +
    • Official release of STM32C0xx CMSIS drivers to support STM32C051xx and STM32C091/92xx devices
      • +
    • General updates to fix known defects and enhance implementation
      • +
    • Align version of bit and registers definition with the STM32C0 reference manual
      • +
    +

    Contents

    +
    • Support of STM32C051xx and STM32C091/92xx devices:
        -
      • Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h” -files
        • -
      • Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s” -and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM -toolchains
        • -
      • Add STM32C051xx and STM32C091/92xx devices linker files for EWARM -and STM32CubeIDE toolchains
        • +
      • Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h” files
        • +
      • Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s” and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains
        • +
      • Add STM32C051xx and STM32C091/92xx devices linker files for EWARM and STM32CubeIDE toolchains
    • Registers and bit field definitions updates :
        -
      • Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware -addresses
        • -
      • Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS -files as undefined
        • +
      • Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware addresses
        • +
      • Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS files as undefined
    -

    Supported Devices

    +

    Supported Devices

      -
    • STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx -and STM32C091/92xx devices
      • +
    • STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx and STM32C091/92xx devices
    - - +
    -

    Main Changes

    +

    Main Changes

      -
    • First official release of STM32C0xx CMSIS drivers to support -STM32C071xx devices
      • +
    • First official release of STM32C0xx CMSIS drivers to support STM32C071xx devices
    • General updates to fix known defects and enhance implementation
      • -
    • Align version of bit and registers definition with the STM32C0 -reference manual
      • +
    • Align version of bit and registers definition with the STM32C0 reference manual
    -

    Contents

    +

    Contents

    • Support of STM32C071xx devices:
      • Add “stm32c071xx.h” file
        • -
      • Add startup files “startup_stm32c071xx.s” for EWARM, STM32CubeIDE -and MDK-ARM toolchains
        • -
      • Add STM32C071xx devices linker files for EWARM and STM32CubeIDE -toolchains
        • +
      • Add startup files “startup_stm32c071xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains
        • +
      • Add STM32C071xx devices linker files for EWARM and STM32CubeIDE toolchains
    • Registers and bit field definitions updates :
        -
      • Add DMAMUX1_RequestGenerator3_BASE and DMAMUX1_RequestGenerator3 -definitions
        • -
      • Remove DMA_IFCR_CGIF4, DMA_IFCR_CTCIF4, DMA_IFCR_CHTIF4 and -DMA_IFCR_CTEIF4 definitions
        • -
      • Add ADC_AWD2CR_AWD2CH_19, ADC_AWD2CR_AWD2CH_20, ADC_AWD2CR_AWD2CH_21 -and ADC_AWD2CR_AWD2CH_22 bits definitions
        • -
      • Add ADC_AWD3CR_AWD3CH_19, ADC_AWD3CR_AWD3CH_20, -ADC_AWD3CR_AWD3CH_21, ADC_AWD3CR_AWD3CH_22 bits definitions
        • +
      • Add DMAMUX1_RequestGenerator3_BASE and DMAMUX1_RequestGenerator3 definitions
        • +
      • Remove DMA_IFCR_CGIF4, DMA_IFCR_CTCIF4, DMA_IFCR_CHTIF4 and DMA_IFCR_CTEIF4 definitions
        • +
      • Add ADC_AWD2CR_AWD2CH_19, ADC_AWD2CR_AWD2CH_20, ADC_AWD2CR_AWD2CH_21 and ADC_AWD2CR_AWD2CH_22 bits definitions
        • +
      • Add ADC_AWD3CR_AWD3CH_19, ADC_AWD3CR_AWD3CH_20, ADC_AWD3CR_AWD3CH_21, ADC_AWD3CR_AWD3CH_22 bits definitions
      • Add FLASH_OPTR_SECURE_MUXING_EN bit definition
      • Correct Flash page number section mask (FLASH_CR_PNB_Msk)
      • Remove extra FLASH_ECCR register bits definitions
        • -
      • Correct masks values of FLASH_PCROP1ASR, FLASH_WRP1AR, FLASH_WRP1BR, -FLASH_WRP1BR, FLASH_PCROP1BER registers
        • +
      • Correct masks values of FLASH_PCROP1ASR, FLASH_WRP1AR, FLASH_WRP1BR, FLASH_WRP1BR, FLASH_PCROP1BER registers
      • Add FLASH_SIZE macro to compute Flash size value
        • -
      • Fix correct FLASH_OPTR_BORF_LEV and FLASH_OPTR_BORR_LEV -positions
        • +
      • Fix correct FLASH_OPTR_BORF_LEV and FLASH_OPTR_BORR_LEV positions
      • Remove SYSCFG_CFGR1_BOOSTEN bit definition
      • Correct SYSCFG_CFGR3 register bits masks values
        • -
      • Change SYSCFG_ITLINE0_SR_EWDG bit definition naming by -SYSCFG_ITLINE0_SR_WWDG to be aligned with the reference manual
        • -
      • Change SYSCFG_ITLINE4_SR_CLK_CTRL bit definition naming by -SYSCFG_ITLINE4_SR_RCC to be aligned with the reference manual
        • +
      • Change SYSCFG_ITLINE0_SR_EWDG bit definition naming by SYSCFG_ITLINE0_SR_WWDG to be aligned with the reference manual
        • +
      • Change SYSCFG_ITLINE4_SR_CLK_CTRL bit definition naming by SYSCFG_ITLINE4_SR_RCC to be aligned with the reference manual
      • Update IS_TIM_REMAP_INSTANCE and IS_TIM_ETRSEL_INSTANCE macros
      • Update TIM Capture/Compare masks values
      • Remove extra EXTI interrupts and events Masks
      • Remove extra PWR_SR2_REGLPF bits definition
      • Update some RCC_CFGR bit definitions
          -
        • Remove RCC_CFGR_MCO2PRE_3 and RCC_CFGR_MCOPRE_3 bits definitions as -reserved
          • -
        • Update RCC_CFGR_MCO2PRE_Msk and RCC_CFGR_MCOPRE_Msk masks -values
          • +
        • Remove RCC_CFGR_MCO2PRE_3 and RCC_CFGR_MCOPRE_3 bits definitions as reserved
          • +
        • Update RCC_CFGR_MCO2PRE_Msk and RCC_CFGR_MCOPRE_Msk masks values
    -

    Supported Devices

    +

    Supported Devices

    • STM32C011xx, STM32C031xx and STM32C071xx devices
    - - -

    Main Changes

    + +
    +

    Main Changes

    Align flash register address with STM32C0 reference manual

    +
    - - -

    Main Changes

    -

    First official release version of bits and registers definition -aligned with STM32C0 reference manual

    + +
    +

    Main Changes

    +

    First official release version of bits and registers definition aligned with STM32C0 reference manual

    +
    +
    -
    -This release note uses up to date web standards and, for this reason, -should not be opened with Internet Explorer but preferably with popular -browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft -Edge. +This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.
    diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.md b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.md new file mode 100644 index 0000000000..14b6f7a494 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.md @@ -0,0 +1,134 @@ + + +# Release Notes for \ STM32C0xx CMSIS +Copyright © 2022\ STMicroelectronics\ + +[![ST logo](_htmresc/st_logo_2020.png)](https://www.st.com) + + +# __Update History__ + + +
    + +## Main Changes + +- General updates to fix known defects and enhance implementation + +## Contents + +- Allow redefinition of the macro 'VECT_TAB_OFFSET' externally from the IDE, makefile, or command line. +- Fix RCC_CSR1_LSEDRV_Msk definition to match actual field width +- Fix DMAMUX1/DMA1 shared interrupt handler name +- Add IAR linker configuration file for STM32C071x8 + +## Supported Devices + +- STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx and STM32C091/92xx devices + +
    + + +
    + +## Main Changes + +- No CMSIS-related fixes were included in this release. + + +
    + + + +
    + +## Main Changes + +- Official release of STM32C0xx CMSIS drivers to support **STM32C051xx** and **STM32C091/92xx** devices +- General updates to fix known defects and enhance implementation +- Align version of bit and registers definition with the STM32C0 reference manual + +## Contents + +- **Support of STM32C051xx and STM32C091/92xx devices**: + - Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h” files + - Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s” and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains + - Add STM32C051xx and STM32C091/92xx devices linker files for EWARM and STM32CubeIDE toolchains + +- **Registers and bit field definitions updates** : + - Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware addresses + - Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS files as undefined + +## Supported Devices + +- STM32C011xx, STM32C031xx, **STM32C051xx**, STM32C071xx and **STM32C091/92xx** devices + +
    + + +
    + +## Main Changes + +- First official release of STM32C0xx CMSIS drivers to support **STM32C071xx** devices +- General updates to fix known defects and enhance implementation +- Align version of bit and registers definition with the STM32C0 reference manual + +## Contents + +- **Support of STM32C071xx devices**: + - Add “stm32c071xx.h” file + - Add startup files “startup_stm32c071xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains + - Add STM32C071xx devices linker files for EWARM and STM32CubeIDE toolchains + +- **Registers and bit field definitions updates** : + - Add DMAMUX1_RequestGenerator3_BASE and DMAMUX1_RequestGenerator3 definitions + - Remove DMA_IFCR_CGIF4, DMA_IFCR_CTCIF4, DMA_IFCR_CHTIF4 and DMA_IFCR_CTEIF4 definitions + - Add ADC_AWD2CR_AWD2CH_19, ADC_AWD2CR_AWD2CH_20, ADC_AWD2CR_AWD2CH_21 and ADC_AWD2CR_AWD2CH_22 bits definitions + - Add ADC_AWD3CR_AWD3CH_19, ADC_AWD3CR_AWD3CH_20, ADC_AWD3CR_AWD3CH_21, ADC_AWD3CR_AWD3CH_22 bits definitions + - Add FLASH_OPTR_SECURE_MUXING_EN bit definition + - Correct Flash page number section mask (FLASH_CR_PNB_Msk) + - Remove extra FLASH_ECCR register bits definitions + - Correct masks values of FLASH_PCROP1ASR, FLASH_WRP1AR, FLASH_WRP1BR, FLASH_WRP1BR, FLASH_PCROP1BER registers + - Add FLASH_SIZE macro to compute Flash size value + - Fix correct FLASH_OPTR_BORF_LEV and FLASH_OPTR_BORR_LEV positions + - Remove SYSCFG_CFGR1_BOOSTEN bit definition + - Correct SYSCFG_CFGR3 register bits masks values + - Change SYSCFG_ITLINE0_SR_EWDG bit definition naming by SYSCFG_ITLINE0_SR_WWDG to be aligned with the reference manual + - Change SYSCFG_ITLINE4_SR_CLK_CTRL bit definition naming by SYSCFG_ITLINE4_SR_RCC to be aligned with the reference manual + - Update IS_TIM_REMAP_INSTANCE and IS_TIM_ETRSEL_INSTANCE macros + - Update TIM Capture/Compare masks values + - Remove extra EXTI interrupts and events Masks + - Remove extra PWR_SR2_REGLPF bits definition + - Update some RCC_CFGR bit definitions + - Remove RCC_CFGR_MCO2PRE_3 and RCC_CFGR_MCOPRE_3 bits definitions as reserved + - Update RCC_CFGR_MCO2PRE_Msk and RCC_CFGR_MCOPRE_Msk masks values + +## Supported Devices + +- STM32C011xx, STM32C031xx and STM32C071xx devices + +
    + + +
    + +## Main Changes + +Align flash register address with STM32C0 reference manual + +
    + + +
    + +## Main Changes + +First official release version of bits and registers definition aligned with STM32C0 reference manual + +
    + + + +This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer +but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s index aed28d0cb6..785ef89c2a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c091xx.s @@ -137,38 +137,38 @@ g_pfnVectors: .word 0 .word PendSV_Handler .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* reserved */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMAMUX1_DMA1_CH4_5_IRQHandler /* DMAMUX1, DMA1 Channel 4 and 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* reserved */ - .word 0 /* reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C1 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI1 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_4_IRQHandler /* USART3 and USART4 */ - .word 0 /* reserved */ - .word 0 /* reserved */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMAMUX1_DMA1_CH4_5_6_7_IRQHandler /* DMAMUX1, DMA1 Channel 4 and 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C1 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI1 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_IRQHandler /* USART3 and USART4 */ + .word 0 /* reserved */ + .word 0 /* reserved */ .size g_pfnVectors, .-g_pfnVectors /******************************************************************************* @@ -221,8 +221,8 @@ g_pfnVectors: .weak DMA1_Channel2_3_IRQHandler .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - .weak DMAMUX1_DMA1_CH4_5_IRQHandler - .thumb_set DMAMUX1_DMA1_CH4_5_IRQHandler,Default_Handler + .weak DMAMUX1_DMA1_CH4_5_6_7_IRQHandler + .thumb_set DMAMUX1_DMA1_CH4_5_6_7_IRQHandler,Default_Handler .weak ADC1_IRQHandler .thumb_set ADC1_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s index 1fa4cd67c0..34b65c0b92 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/startup_stm32c092xx.s @@ -137,38 +137,38 @@ g_pfnVectors: .word 0 .word PendSV_Handler .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* reserved */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMAMUX1_DMA1_CH4_5_IRQHandler /* DMAMUX1, DMA1 Channel 4 and 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* reserved */ - .word 0 /* reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C1 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI1 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_4_IRQHandler /* USART3 and USART4 */ - .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt request 0 pending */ - .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt request 1 pending */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMAMUX1_DMA1_CH4_5_6_7_IRQHandler /* DMAMUX1, DMA1 Channel 4 and 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C1 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI1 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_IRQHandler /* USART3 and USART4 */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt request 0 pending */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt request 1 pending */ .size g_pfnVectors, .-g_pfnVectors /******************************************************************************* @@ -221,8 +221,8 @@ g_pfnVectors: .weak DMA1_Channel2_3_IRQHandler .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - .weak DMAMUX1_DMA1_CH4_5_IRQHandler - .thumb_set DMAMUX1_DMA1_CH4_5_IRQHandler,Default_Handler + .weak DMAMUX1_DMA1_CH4_5_6_7_IRQHandler + .thumb_set DMAMUX1_DMA1_CH4_5_6_7_IRQHandler,Default_Handler .weak ADC1_IRQHandler .thumb_set ADC1_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/system_stm32c0xx.c b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/system_stm32c0xx.c index 66a8821ee9..f4c73b6742 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/system_stm32c0xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/system_stm32c0xx.c @@ -87,8 +87,12 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ //#define VECT_TAB_SRAM +#if !defined(VECT_TAB_OFFSET) + #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. This value must be a multiple of 0x100. */ + +#endif /* VECT_TAB_OFFSET */ /******************************************************************************/ /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 622c0f12a0..446b86d20a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -1,6 +1,6 @@ # STM32YYxx CMSIS version: - * STM32C0: 1.3.0 + * STM32C0: 1.4.1 * STM32C5: 2.1.0 * STM32F0: 2.3.7 * STM32F1: 4.3.5