diff --git a/PCB/diagrams/power_control_layout.html b/PCB/diagrams/power_control_layout.html
index 35b21cb..478cdc5 100644
--- a/PCB/diagrams/power_control_layout.html
+++ b/PCB/diagrams/power_control_layout.html
@@ -276,11 +276,11 @@ <h2>What's on this sheet</h2>
     <tbody>
       <tr><td class="ref">Q_PWR1</td><td class="val">DMG2305UX</td><td class="val">SOT-23</td><td class="role">Main power switch — VSYS to PWR_EN, carries full system current</td></tr>
       <tr><td class="ref">R_PWR_EN_PD1</td><td class="val">100kΩ</td><td class="val">0402</td><td class="role">PWR_EN pull-down to GND — the buck's EN pin has no internal bias and must not be left floating (callout G)</td></tr>
-      <tr><td class="ref">Q_LATCH1</td><td class="val">2N7002</td><td class="val">SOT-23</td><td class="role">Pulls Q_PWR1's gate low to turn it on</td></tr>
+      <tr><td class="ref">Q_LATCH1</td><td class="val">AO3400A</td><td class="val">SOT-23</td><td class="role">Pulls Q_PWR1's gate low to turn it on; low-Vth (≤1.45V) so a press still turns it on at the bottom of the battery range (callout D)</td></tr>
       <tr><td class="ref">D_OR1 / D_OR2</td><td class="val">1N4148W</td><td class="val">SOD-123</td><td class="role">Diode-OR: PWR_BTN_TRIGGER (actual button press, via the inverter) or MCU hold, either one latches power on</td></tr>
       <tr><td class="ref">R_GATE1</td><td class="val">100kΩ</td><td class="val">0402</td><td class="role">Q_PWR1 gate pull-up — off by default</td></tr>
       <tr><td class="ref">R_LATCH_G1</td><td class="val">1MΩ</td><td class="val">0402</td><td class="role">Q_LATCH1 gate pull-down — off by default; sized to not starve the diode-OR's drive (callout D)</td></tr>
-      <tr><td class="ref">R_BTN_PU1</td><td class="val">100kΩ</td><td class="val">0402</td><td class="role">Button sense pull-up — MCU reads pressed (0V) vs idle (VSYS)</td></tr>
+      <tr><td class="ref">R_BTN_PU1</td><td class="val">100kΩ</td><td class="val">0402</td><td class="role">Button sense pull-up to 3V3 (not VSYS) — MCU reads pressed (0V) vs idle (3.3V); callout H</td></tr>
       <tr><td class="ref">R_INV_BASE1</td><td class="val">100kΩ</td><td class="val">0402</td><td class="role">Dedicated VSYS pull-up for Q_INV1's base — decoupled from PWR_BTN_SENSE (callout F)</td></tr>
       <tr><td class="ref">D_INV_ISO1</td><td class="val">BAT54W</td><td class="val">SOD-123</td><td class="role">Schottky isolator: lets a press pull Q_INV1's base low without loading PWR_BTN_SENSE</td></tr>
       <tr><td class="ref">Q_INV1</td><td class="val">MMBT3904</td><td class="val">SOT-23</td><td class="role">Inverter: idle (button up) holds PWR_BTN_TRIGGER low; pressed lets R_INV_PU1 pull it high</td></tr>
@@ -399,7 +399,7 @@ <h2>Suggested floorplan</h2>
         <!-- Q_LATCH1 -->
         <rect x="195" y="250" width="30" height="50" rx="4" fill="#20241f" stroke="#4a5044" stroke-width="1.5"/>
         <text x="210" y="243" text-anchor="middle" font-family="JetBrains Mono, monospace" font-weight="700" font-size="11" fill="#e0b563">Q_LATCH1</text>
-        <text x="210" y="315" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="9" fill="#7fa08d">2N7002 (NMOS)</text>
+        <text x="210" y="315" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="9" fill="#7fa08d">AO3400A (NMOS)</text>
         <text x="238" y="279" text-anchor="start" font-family="JetBrains Mono, monospace" font-size="9" fill="#c9d6cd">G</text>
 
         <!-- R_LATCH_G1 -->
@@ -429,7 +429,7 @@ <h2>Suggested floorplan</h2>
 
         <!-- R_BTN_PU1 -->
         <rect x="273" y="408" width="14" height="26" rx="2" fill="#20241f" stroke="#4a5044" stroke-width="1.5"/>
-        <text x="262" y="382" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="10" fill="#e0b563">VSYS</text>
+        <text x="262" y="382" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="10" fill="#e0b563">3V3</text>
         <text x="292" y="425" text-anchor="start" font-family="JetBrains Mono, monospace" font-size="9.5" fill="#8fd3ff">R_BTN_PU1 100k</text>
 
         <!-- D_INV_ISO1: isolates Q_INV1's base pull-up from PWR_BTN_SENSE so
@@ -529,10 +529,11 @@ <h2>Why it's arranged this way</h2>
     <li><span class="badge">A</span><p><b>Q_PWR1 is the one part on this sheet that isn't low-current.</b> Every downstream milliamp — MCU, XBee, OLED, everything — flows through its source-drain path. DMG2305UX's RDS(on) (~35–50mΩ) keeps drop and heat trivial at this board's current budget, but a SOT-23 has no separate thermal pad — the source/drain copper itself is the heatsink, so give those pads real copper, not just a skinny trace.</p></li>
     <li><span class="badge">B</span><p><b>SW_PWR1's position isn't yours to optimize electrically.</b> It has to land under a hole in whatever enclosure this board sits in — mechanical placement drives this part, and the rest of the latch logic has to route to wherever that ends up, not the other way around.</p></li>
     <li><span class="badge">C</span><p><b>C_DBNC1 sits right on the switch's own pins.</b> Same principle as the charger's pushbutton guidance in its own datasheet: the debounce cap does its job by being close to the contact bounce it's filtering, not by being close to anything else.</p></li>
-    <li><span class="badge">D</span><p><b>The diode-OR and its pull-down are one compact decision node — and R_LATCH_G1's value is load-bearing, not incidental.</b> D_OR1, D_OR2, R_LATCH_G1, and Q_LATCH1's gate all meet at PWR_LATCH_G. A press only drives this node through R_INV_PU1 (100kΩ) and a diode drop — with the original 10kΩ pull-down, that divider left barely 0.3V at Q_LATCH1's gate, nowhere near enough to turn it on. Raised to 1MΩ, the same divider delivers ~2.4–3.1V across the battery's usable range, without adding any idle current (that's set by R_INV_PU1, untouched). Keeping this cluster tight matters less for noise than for just keeping the logic legible on the board.</p></li>
+    <li><span class="badge">D</span><p><b>The diode-OR and its pull-down are one compact decision node — and R_LATCH_G1's value is load-bearing, not incidental.</b> D_OR1, D_OR2, R_LATCH_G1, and Q_LATCH1's gate all meet at PWR_LATCH_G. A press only drives this node through R_INV_PU1 (100kΩ) and a diode drop — with the original 10kΩ pull-down, that divider left barely 0.3V at Q_LATCH1's gate, nowhere near enough to turn it on. Raised to 1MΩ, the same divider delivers ~2.4V at the bottom of the battery range (VSYS≈3.0V, modelling a real ~0.35V diode drop at µA currents) up to ~3.5V at full charge, without adding any idle current (that's set by R_INV_PU1, untouched). A 2N7002's worst-case threshold is 2.5V, which left no margin at the bottom, so Q_LATCH1 is an AO3400A (Vgs(th) ≤1.45V): at least ~1V of overdrive everywhere. Keeping this cluster tight matters less for noise than for just keeping the logic legible on the board.</p></li>
     <li><span class="badge">E</span><p><b>PWR_HOLD arriving late is a hard failure, not a glitch.</b> Per this project's own GPIO notes, pin 36 (PWR_HOLD) must go high as the MCU's very first instruction — release the button before that happens and R_LATCH_G1's pull-down turns everything back off. Not a layout fix, but it's the reason D_OR2's path exists at all.</p></li>
     <li><span class="badge">F</span><p><b>D_OR1 can't read PWR_BTN_SENSE directly — found the hard way, on real hardware.</b> The original design had R_BTN_PU1 (to VSYS) and a since-removed R_PWR_SENSE1 (to GND) both on that node, dividing it to roughly half VSYS at idle — comfortably above a diode's ~0.6V forward threshold, so D_OR1 was forward-biased (and the board powered on) the instant a battery was plugged in, button or no button. The inverter fixes this properly instead of just retuning the divider: idle, Q_INV1 is on and holds PWR_BTN_TRIGGER at GND; pressed, it turns off and R_INV_PU1 pulls PWR_BTN_TRIGGER to VSYS. Only a real press can forward-bias D_OR1 now. Keep this block close to D_OR1 — it's parts serving one signal, not worth spreading out.<br><br><b>Second-order bug, found the same way:</b> the inverter's own base resistor originally tapped PWR_BTN_SENSE directly, in series with R_BTN_PU1 — stealing enough idle base current to sag the MCU's own button-read node to ~1V instead of near-VSYS. R_INV_BASE1 is now its own dedicated 100kΩ pull-up straight to VSYS (not sharing current with R_BTN_PU1), and D_INV_ISO1 (a Schottky, chosen specifically for its lower forward drop than Q_INV1's own base-emitter junction) lets a press still pull the base low without ever loading PWR_BTN_SENSE.</p></li>
     <li><span class="badge">G</span><p><b>PWR_EN had no defined rest state — TI's own datasheet says not to do this.</b> Q_PWR1's drain feeds the buck's EN pin directly, with nothing else on that node. TLV62569's EN pin is a bare comparator input with no internal pull ("Do not leave floating" per its datasheet) — with Q_PWR1 off, EN was held by MOSFET/input leakage alone, no guaranteed logic level. R_PWR_EN_PD1 (100kΩ to GND) fixes it: negligible loading when Q_PWR1's tens-of-mΩ RDS(on) is driving EN high, solid GND the instant it's off.</p></li>
+    <li><span class="badge">H</span><p><b>PWR_BTN_SENSE must never sit above the MCU's rail.</b> It lands directly on GPIO2 (pin 38), whose ceiling is VDD + 0.3V (~3.6V), but R_BTN_PU1 used to pull it to VSYS — up to ~4.5V on USB, and it back-fed the unpowered 3V3 rail through the pin's clamp diode whenever the MCU was off. Since R_INV_BASE1 gave the inverter its own VSYS pull-up (callout F), R_BTN_PU1 no longer has to supply the inverter, so it now pulls to 3V3: idle reads 3.3V, and with the MCU off the node is simply unpowered instead of leaking into the rail.</p></li>
   </ol>
 </section>
 
diff --git a/PCB/diagrams/power_control_layout.md b/PCB/diagrams/power_control_layout.md
index 25ad1f0..2527503 100644
--- a/PCB/diagrams/power_control_layout.md
+++ b/PCB/diagrams/power_control_layout.md
@@ -14,11 +14,11 @@ A press-to-start, software-held latch: the button turns the board on, the MCU ha
 |---|---|---|---|
 | Q_PWR1 | DMG2305UX | SOT-23 | Main power switch — VSYS to PWR_EN, carries full system current |
 | R_PWR_EN_PD1 | 100kΩ | 0402 | `PWR_EN` pull-down to GND — the buck's EN pin has no internal bias and must not be left floating (callout G) |
-| Q_LATCH1 | 2N7002 | SOT-23 | Pulls Q_PWR1's gate low to turn it on |
+| Q_LATCH1 | AO3400A | SOT-23 | Pulls Q_PWR1's gate low to turn it on; low-Vth (≤1.45V) so a press still turns it on at the bottom of the battery range (callout D) |
 | D_OR1 / D_OR2 | 1N4148W | SOD-123 | Diode-OR: `PWR_BTN_TRIGGER` (actual button press, via the inverter) or MCU hold, either one latches power on |
 | R_GATE1 | 100kΩ | 0402 | Q_PWR1 gate pull-up — off by default |
 | R_LATCH_G1 | 1MΩ | 0402 | Q_LATCH1 gate pull-down — off by default; sized to not starve the diode-OR's drive (callout D) |
-| R_BTN_PU1 | 100kΩ | 0402 | Button sense pull-up — MCU reads pressed (0V) vs idle (VSYS) |
+| R_BTN_PU1 | 100kΩ | 0402 | Button sense pull-up to **3V3** (not VSYS) — MCU reads pressed (0V) vs idle (3.3V); callout H |
 | R_INV_BASE1 | 100kΩ | 0402 | Dedicated VSYS pull-up for Q_INV1's base — decoupled from `PWR_BTN_SENSE` (callout F) |
 | D_INV_ISO1 | BAT54W | SOD-123 | Schottky isolator: lets a press pull Q_INV1's base low without loading `PWR_BTN_SENSE` |
 | Q_INV1 | MMBT3904 | SOT-23 | Inverter: idle (button up) holds `PWR_BTN_TRIGGER` low; pressed lets `R_INV_PU1` pull it high |
@@ -45,10 +45,11 @@ Top copper layer. The VSYS→PWR_EN path runs straight across the top as one thi
 | **A** | **Q_PWR1 is the one part on this sheet that isn't low-current.** Every downstream milliamp — MCU, XBee, OLED, everything — flows through its source-drain path. DMG2305UX's RDS(on) (~35–50mΩ) keeps drop and heat trivial at this board's current budget, but a SOT-23 has no separate thermal pad — the source/drain copper itself is the heatsink, so give those pads real copper, not just a skinny trace. |
 | **B** | **SW_PWR1's position isn't yours to optimize electrically.** It has to land under a hole in whatever enclosure this board sits in — mechanical placement drives this part, and the rest of the latch logic has to route to wherever that ends up, not the other way around. |
 | **C** | **C_DBNC1 sits right on the switch's own pins.** Same principle as the charger's pushbutton guidance in its own datasheet: the debounce cap does its job by being close to the contact bounce it's filtering, not by being close to anything else. |
-| **D** | **The diode-OR and its pull-down are one compact decision node — and R_LATCH_G1's value is load-bearing, not incidental.** D_OR1, D_OR2, R_LATCH_G1, and Q_LATCH1's gate all meet at PWR_LATCH_G. A press only drives this node through `R_INV_PU1` (100kΩ) and a diode drop — with the original 10kΩ pull-down, that divider left barely 0.3V at Q_LATCH1's gate, nowhere near enough to turn it on. Raised to 1MΩ, the same divider delivers ~2.4–3.1V across the battery's usable range, without adding any idle current (that's set by `R_INV_PU1`, untouched). Keeping this cluster tight matters less for noise than for just keeping the logic legible on the board. |
+| **D** | **The diode-OR and its pull-down are one compact decision node — and R_LATCH_G1's value is load-bearing, not incidental.** D_OR1, D_OR2, R_LATCH_G1, and Q_LATCH1's gate all meet at PWR_LATCH_G. A press only drives this node through `R_INV_PU1` (100kΩ) and a diode drop — with the original 10kΩ pull-down, that divider left barely 0.3V at Q_LATCH1's gate, nowhere near enough to turn it on. Raised to 1MΩ, the same divider delivers ~2.4V at the bottom of the battery range (VSYS≈3.0V, modelling a real ~0.35V diode drop at µA currents) up to ~3.5V at full charge, without adding any idle current (that's set by `R_INV_PU1`, untouched). A 2N7002's worst-case threshold is 2.5V, which left no margin at the bottom, so `Q_LATCH1` is an AO3400A (Vgs(th) ≤1.45V): at least ~1V of overdrive everywhere. Keeping this cluster tight matters less for noise than for just keeping the logic legible on the board. |
 | **E** | **PWR_HOLD arriving late is a hard failure, not a glitch.** Per this project's own GPIO notes, pin 36 (PWR_HOLD) must go high as the MCU's very first instruction — release the button before that happens and R_LATCH_G1's pull-down turns everything back off. Not a layout fix, but it's the reason D_OR2's path exists at all. |
 | **F** | **D_OR1 can't read `PWR_BTN_SENSE` directly — found the hard way, on real hardware.** The original design had `R_BTN_PU1` (to VSYS) and a since-removed `R_PWR_SENSE1` (to GND) both on that node, dividing it to roughly half VSYS at idle — comfortably above a diode's ~0.6V forward threshold, so `D_OR1` was forward-biased (and the board powered on) the instant a battery was plugged in, button or no button. The inverter fixes this properly instead of just retuning the divider: idle, `Q_INV1` is on and holds `PWR_BTN_TRIGGER` at GND; pressed, it turns off and `R_INV_PU1` pulls `PWR_BTN_TRIGGER` to VSYS. Only a real press can forward-bias `D_OR1` now. Keep this block close to `D_OR1` — it's parts serving one signal, not worth spreading out.<br><br>**Second-order bug, found the same way:** the inverter's own base resistor originally tapped `PWR_BTN_SENSE` directly, in series with `R_BTN_PU1` — stealing enough idle base current to sag the MCU's own button-read node to ~1V instead of near-VSYS. `R_INV_BASE1` is now its own dedicated 100kΩ pull-up straight to VSYS (not sharing current with `R_BTN_PU1`), and `D_INV_ISO1` (a Schottky, chosen specifically for its lower forward drop than Q_INV1's own base-emitter junction) lets a press still pull the base low without ever loading `PWR_BTN_SENSE`. |
 | **G** | **`PWR_EN` had no defined rest state — TI's own datasheet says not to do this.** `Q_PWR1`'s drain feeds the buck's EN pin directly, with nothing else on that node. TLV62569's EN pin is a bare comparator input with no internal pull ("Do not leave floating" per its datasheet) — with `Q_PWR1` off, EN was held by MOSFET/input leakage alone, no guaranteed logic level. `R_PWR_EN_PD1` (100kΩ to GND) fixes it: negligible loading when `Q_PWR1`'s tens-of-mΩ RDS(on) is driving EN high, solid GND the instant it's off. |
+| **H** | **`PWR_BTN_SENSE` must never sit above the MCU's rail.** It lands directly on GPIO2 (pin 38), whose ceiling is VDD + 0.3V (~3.6V), but `R_BTN_PU1` used to pull it to VSYS — up to ~4.5V on USB, and it back-fed the unpowered 3V3 rail through the pin's clamp diode whenever the MCU was off. Since `R_INV_BASE1` gave the inverter its own VSYS pull-up (callout F), `R_BTN_PU1` no longer has to supply the inverter, so it now pulls to 3V3: idle reads 3.3V, and with the MCU off the node is simply unpowered instead of leaking into the rail. |
 
 ## Routing priority
 
diff --git a/PCB/diagrams/power_control_layout.svg b/PCB/diagrams/power_control_layout.svg
index b3ea530..0e11f05 100644
--- a/PCB/diagrams/power_control_layout.svg
+++ b/PCB/diagrams/power_control_layout.svg
@@ -99,7 +99,7 @@
         <!-- Q_LATCH1 -->
         <rect x="195" y="250" width="30" height="50" rx="4" fill="#20241f" stroke="#4a5044" stroke-width="1.5"/>
         <text x="210" y="243" text-anchor="middle" font-family="JetBrains Mono, monospace" font-weight="700" font-size="11" fill="#e0b563">Q_LATCH1</text>
-        <text x="210" y="315" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="9" fill="#7fa08d">2N7002 (NMOS)</text>
+        <text x="210" y="315" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="9" fill="#7fa08d">AO3400A (NMOS)</text>
         <text x="238" y="279" text-anchor="start" font-family="JetBrains Mono, monospace" font-size="9" fill="#c9d6cd">G</text>
 
         <!-- R_LATCH_G1 -->
@@ -129,7 +129,7 @@
 
         <!-- R_BTN_PU1 -->
         <rect x="273" y="408" width="14" height="26" rx="2" fill="#20241f" stroke="#4a5044" stroke-width="1.5"/>
-        <text x="262" y="382" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="10" fill="#e0b563">VSYS</text>
+        <text x="262" y="382" text-anchor="middle" font-family="JetBrains Mono, monospace" font-size="10" fill="#e0b563">3V3</text>
         <text x="292" y="425" text-anchor="start" font-family="JetBrains Mono, monospace" font-size="9.5" fill="#8fd3ff">R_BTN_PU1 100k</text>
 
         <!-- D_INV_ISO1: isolates Q_INV1's base pull-up from PWR_BTN_SENSE so
diff --git a/PCB/power_control.kicad_sch b/PCB/power_control.kicad_sch
index 10fb996..e1852fa 100644
--- a/PCB/power_control.kicad_sch
+++ b/PCB/power_control.kicad_sch
@@ -1741,7 +1741,7 @@
 			)
 		)
 	)
-	(global_label "VSYS"
+	(global_label "3V3"
 		(shape input)
 		(at 156.21 134.62 90)
 		(fields_autoplaced yes)
@@ -3499,7 +3499,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "2N7002"
+		(property "Value" "AO3400A"
 			(at 194.31 127 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -3540,7 +3540,7 @@
 				)
 			)
 		)
-		(property "MF" "Jiangsu Changjing Electronics Technology Co., Ltd."
+		(property "MF" "Alpha & Omega Semicon"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -3551,7 +3551,7 @@
 				)
 			)
 		)
-		(property "Manufacturer_Part_Number" "2N7002"
+		(property "Manufacturer_Part_Number" "AO3400A"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -3562,7 +3562,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C8545"
+		(property "LCSC" "C20917"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
diff --git a/PCB/production/bom/snips_controller-bom.csv b/PCB/production/bom/snips_controller-bom.csv
index bfe942e..63bda09 100644
--- a/PCB/production/bom/snips_controller-bom.csv
+++ b/PCB/production/bom/snips_controller-bom.csv
@@ -17,7 +17,7 @@
 16;"J_USB1";"USB_C_Receptacle_HRO_TYPE-C-31-M-12";1;"USB-C";;;
 17;"L_BUCK1";"L_Bourns-SRN4018";1;"2.2µH";;;
 18;"Q_INV1";"SOT-23";1;"MMBT3904";;;
-19;"Q_LATCH1";"SOT-23";1;"2N7002";;;
+19;"Q_LATCH1";"SOT-23";1;"AO3400A";;;
 20;"Q_PWR1";"SOT-23";1;"AO3401A";;;
 21;"R_BOOT_PU1, R_EN_PU1, R_STAT1, R_STAT2, R_TS1, R_XBEE_ATTN_PU1, R_XBEE_RST1";"R_0402_1005Metric";7;"10kΩ";;;
 22;"R_BTN_PU1, R_GATE1, R_INV_BASE1, R_INV_PU1, R_PWR_EN_PD1, R_VSYS2";"R_0402_1005Metric";6;"100kΩ";;;
diff --git a/PCB/production/gerbers/snips_controller-B_Cu.gbr b/PCB/production/gerbers/snips_controller-B_Cu.gbr
index 6a1bcd9..6f77dca 100644
--- a/PCB/production/gerbers/snips_controller-B_Cu.gbr
+++ b/PCB/production/gerbers/snips_controller-B_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:47-07:00*%
+%TF.CreationDate,2026-09-23T21:17:53-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L4,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:47*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53*
 %MOMM*%
 %LPD*%
 G01*
@@ -135,13 +135,13 @@ G04 Aperture macros list end*
 %ADD41C,0.600000*%
 %TD*%
 %TA.AperFunction,Conductor*%
-%ADD42C,0.300000*%
+%ADD42C,0.200000*%
 %TD*%
 %TA.AperFunction,Conductor*%
-%ADD43C,0.550000*%
+%ADD43C,0.300000*%
 %TD*%
 %TA.AperFunction,Conductor*%
-%ADD44C,0.200000*%
+%ADD44C,0.550000*%
 %TD*%
 %TA.AperFunction,Conductor*%
 %ADD45C,0.800000*%
@@ -260,7 +260,7 @@ X140750000Y-105500000D03*
 %TD*%
 D16*
 %TO.P,R_BTN_PU1,1*%
-%TO.N,VSYS*%
+%TO.N,3V3*%
 X149170000Y-133700000D03*
 %TO.P,R_BTN_PU1,2*%
 %TO.N,/MCU_Core/PWR_BTN_SENSE*%
@@ -652,6 +652,7 @@ X125000000Y-124000000D03*
 %TD*%
 D41*
 %TO.N,3V3*%
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@@ -695,7 +696,6 @@ X139500000Y-118500000D03*
 X149800000Y-150800000D03*
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-X149950000Y-134800000D03*
 X145000000Y-123500000D03*
 X145250000Y-65100000D03*
 X123500000Y-124000000D03*
@@ -732,11 +732,6 @@ X145000000Y-78500000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO6*%
 X148500000Y-90302943D03*
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-%TO.N,/Power_Buck/PWR_EN*%
-X149000000Y-112000000D03*
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 %TO.N,/Buttons_Direct/BTN_MACRO3*%
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@@ -811,17 +806,42 @@ X143600000Y-124150000D03*
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-%TO.N,3V3*%
+%TO.N,/MCU_Core/PWR_BTN_SENSE*%
 D42*
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@@ -836,30 +856,30 @@ X152700000Y-65300000D02*
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@@ -894,10 +914,10 @@ X140050000Y-77250000D02*
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@@ -958,23 +978,23 @@ X148500000Y-120000000D02*
 X147500000Y-119000000D01*
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 X138650000Y-76850000D01*
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@@ -983,19 +1003,17 @@ X139900000Y-118100000D02*
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 X133450000Y-120070634D02*
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 X138650000Y-76150000D02*
@@ -1106,27 +1124,6 @@ X146500000Y-88302943D02*
 X148500000Y-90302943D01*
 X146500000Y-78500000D02*
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-%TO.N,/Power_Buck/PWR_EN*%
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 %TO.N,/Buttons_Direct/BTN_MACRO3*%
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 X148100000Y-92746167D01*
@@ -1371,7 +1368,7 @@ X136999999Y-122096015D01*
 X135700000Y-119884314D02*
 X135700000Y-121410000D01*
 %TO.N,/MCU_Core/PWR_HOLD*%
-D42*
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@@ -1389,7 +1386,7 @@ X140400000Y-89680761D01*
 X144150000Y-85930761D02*
 X144150000Y-80634925D01*
 %TO.N,/MCU_Core/RGB_DIN*%
-D44*
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 X151500000Y-85000000D02*
 X151500000Y-78000000D01*
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@@ -1397,38 +1394,24 @@ X145980000Y-137500000D02*
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-X148140000Y-134850000D01*
 X136480000Y-147000000D02*
 X125063866Y-147000000D01*
 %TO.N,/MCU_Core/STAT1*%
@@ -1505,10 +1488,10 @@ X124751471Y-155100000D02*
 X122584500Y-152933029D01*
 X138200000Y-154350000D02*
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 X133065500Y-150965500D02*
@@ -1532,8 +1515,6 @@ X123488235Y-87388235D02*
 X123488235Y-100336764D01*
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@@ -1544,16 +1525,16 @@ X143500652Y-120800652D02*
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 X134600000Y-117000000D02*
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 X134050000Y-117550000D02*
 X134600000Y-117000000D01*
 X148625000Y-116050000D02*
@@ -1578,10 +1559,10 @@ X147900000Y-113880000D02*
 X148520000Y-114500000D01*
 X123488235Y-100336764D02*
 X127626471Y-104475000D01*
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 X143100000Y-123950000D02*
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@@ -1592,8 +1573,6 @@ X134050000Y-118200000D02*
 X134050000Y-117550000D01*
 X136275000Y-108200000D02*
 X134400000Y-108200000D01*
-X150250000Y-131660000D02*
-X150250000Y-132620000D01*
 %TO.N,/Power_Control/PWR_GATE*%
 X147500000Y-116825000D02*
 X148625000Y-117950000D01*
@@ -1603,18 +1582,39 @@ X148625000Y-117950000D02*
 X150375000Y-119700000D01*
 X147500000Y-114500000D02*
 X147500000Y-116825000D01*
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 %TO.N,VBAT*%
-D43*
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 X152500000Y-71000000D02*
 X152400000Y-71100000D01*
 X139821016Y-120775000D02*
 X139608884Y-120775000D01*
 X152400000Y-98978858D02*
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 X136500000Y-120500000D02*
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-D43*
+D44*
 X152400000Y-102071142D02*
 X152225000Y-102246142D01*
 X152400000Y-97821142D02*
@@ -1627,10 +1627,10 @@ X152225000Y-92221142D02*
 X152225000Y-93028858D01*
 X152225000Y-87971142D02*
 X152225000Y-88778858D01*
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 X136500000Y-119775000D02*
 X135325000Y-118600000D01*
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+D44*
 X139375000Y-121008884D02*
 X139375000Y-121282232D01*
 X152225000Y-98803858D02*
@@ -1671,16 +1671,16 @@ X152500000Y-68900000D02*
 X152500000Y-71000000D01*
 X152400000Y-92046142D02*
 X152225000Y-92221142D01*
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 X135325000Y-118600000D02*
 X134050000Y-118600000D01*
-D43*
+D44*
 X139375000Y-121282232D02*
 X138957232Y-121700000D01*
 X152400000Y-107100000D02*
 X141000000Y-118500000D01*
 %TO.N,/Power_Control/PWR_BTN_INV_BASE*%
-D44*
+D42*
 X146100000Y-129400000D02*
 X147900000Y-129400000D01*
 X145850000Y-129150000D02*
@@ -1775,7 +1775,7 @@ X131000000Y-119439070D01*
 X131439071Y-119000000D02*
 X131950000Y-119000000D01*
 %TO.N,/Power_Buck/BUCK_FB*%
-D42*
+D43*
 X134500000Y-109800000D02*
 X134500000Y-112000000D01*
 X132425000Y-107725000D02*
diff --git a/PCB/production/gerbers/snips_controller-B_Mask.gbr b/PCB/production/gerbers/snips_controller-B_Mask.gbr
index 10317f2..2fb8d06 100644
--- a/PCB/production/gerbers/snips_controller-B_Mask.gbr
+++ b/PCB/production/gerbers/snips_controller-B_Mask.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:48-07:00*%
+%TF.CreationDate,2026-09-23T21:17:54-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Soldermask,Bot*%
 %TF.FilePolarity,Negative*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:48*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/production/gerbers/snips_controller-B_Paste.gbr b/PCB/production/gerbers/snips_controller-B_Paste.gbr
index 9387c2a..a8bc48f 100644
--- a/PCB/production/gerbers/snips_controller-B_Paste.gbr
+++ b/PCB/production/gerbers/snips_controller-B_Paste.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:47-07:00*%
+%TF.CreationDate,2026-09-23T21:17:54-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Paste,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:47*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr b/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr
index 0febd88..53e9ffd 100644
--- a/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr
+++ b/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:48-07:00*%
+%TF.CreationDate,2026-09-23T21:17:54-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Legend,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:48*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr b/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr
index 1dc6296..a165cda 100644
--- a/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr
+++ b/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr
@@ -1,11 +1,11 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:48-07:00*%
+%TF.CreationDate,2026-09-23T21:17:54-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Profile,NP*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:48*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/production/gerbers/snips_controller-F_Cu.gbr b/PCB/production/gerbers/snips_controller-F_Cu.gbr
index 3d43bdc..4dc8a4a 100644
--- a/PCB/production/gerbers/snips_controller-F_Cu.gbr
+++ b/PCB/production/gerbers/snips_controller-F_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:47-07:00*%
+%TF.CreationDate,2026-09-23T21:17:53-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L1,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:47*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53*
 %MOMM*%
 %LPD*%
 G01*
@@ -168,10 +168,10 @@ G04 Aperture macros list end*
 %ADD55C,0.200000*%
 %TD*%
 %TA.AperFunction,Conductor*%
-%ADD56C,0.550000*%
+%ADD56C,0.300000*%
 %TD*%
 %TA.AperFunction,Conductor*%
-%ADD57C,0.300000*%
+%ADD57C,0.550000*%
 %TD*%
 G04 APERTURE END LIST*
 D10*
@@ -898,6 +898,7 @@ X150160000Y-63000000D03*
 %TD*%
 D54*
 %TO.N,3V3*%
+X149550000Y-132950000D03*
 X139342332Y-122557668D03*
 X122500000Y-107500000D03*
 X127110000Y-120400000D03*
@@ -941,7 +942,6 @@ X139500000Y-118500000D03*
 X149800000Y-150800000D03*
 X134700000Y-119750000D03*
 X139500000Y-88000000D03*
-X149950000Y-134800000D03*
 X145000000Y-123500000D03*
 X145250000Y-65100000D03*
 X123500000Y-124000000D03*
@@ -978,11 +978,6 @@ X145000000Y-78500000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO6*%
 X148500000Y-90302943D03*
 X145000000Y-77000000D03*
-%TO.N,/Power_Buck/PWR_EN*%
-X149000000Y-112000000D03*
-X133588870Y-113975000D03*
-X143000000Y-114500000D03*
-X133850000Y-111000000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO3*%
 X145500000Y-80500000D03*
 X145000000Y-109500000D03*
@@ -1057,6 +1052,11 @@ X143600000Y-124150000D03*
 X136275000Y-108200000D03*
 X149350000Y-130760000D03*
 X139000000Y-119124499D03*
+%TO.N,/Power_Buck/PWR_EN*%
+X149000000Y-112000000D03*
+X133588870Y-113975000D03*
+X143000000Y-114500000D03*
+X133850000Y-111000000D03*
 %TD*%
 %TO.N,3V3*%
 D55*
@@ -1684,22 +1684,7 @@ X153350000Y-112748529D02*
 X147698529Y-118400000D01*
 X145000000Y-76880000D02*
 X145000000Y-77000000D01*
-%TO.N,/Power_Buck/PWR_EN*%
-D56*
-X149000000Y-112000000D02*
-X146500000Y-114500000D01*
-X146500000Y-114500000D02*
-X143000000Y-114500000D01*
-X133613870Y-111000000D02*
-X133850000Y-111000000D01*
-X133025000Y-111588870D02*
-X133613870Y-111000000D01*
-X133588870Y-113975000D02*
-X133025000Y-113411130D01*
-X133025000Y-113411130D02*
-X133025000Y-111588870D01*
 %TO.N,/Buttons_Direct/BTN_MACRO3*%
-D55*
 X146110000Y-79890000D02*
 X145500000Y-80500000D01*
 X144750000Y-109750000D02*
@@ -2098,7 +2083,7 @@ X136300000Y-74850000D01*
 X136999999Y-122096015D02*
 X138000000Y-121096014D01*
 %TO.N,/MCU_Core/PWR_HOLD*%
-D57*
+D56*
 X139150000Y-113957107D02*
 X141992893Y-116800000D01*
 X146380000Y-70100000D02*
@@ -2290,5 +2275,19 @@ X149350000Y-129701471D02*
 X149350000Y-130760000D01*
 X143798529Y-124150000D02*
 X149350000Y-129701471D01*
+%TO.N,/Power_Buck/PWR_EN*%
+D57*
+X149000000Y-112000000D02*
+X146500000Y-114500000D01*
+X146500000Y-114500000D02*
+X143000000Y-114500000D01*
+X133613870Y-111000000D02*
+X133850000Y-111000000D01*
+X133025000Y-111588870D02*
+X133613870Y-111000000D01*
+X133588870Y-113975000D02*
+X133025000Y-113411130D01*
+X133025000Y-113411130D02*
+X133025000Y-111588870D01*
 %TD*%
 M02*
diff --git a/PCB/production/gerbers/snips_controller-F_Mask.gbr b/PCB/production/gerbers/snips_controller-F_Mask.gbr
index c0a0b0b..17641c0 100644
--- a/PCB/production/gerbers/snips_controller-F_Mask.gbr
+++ b/PCB/production/gerbers/snips_controller-F_Mask.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:48-07:00*%
+%TF.CreationDate,2026-09-23T21:17:54-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Soldermask,Top*%
 %TF.FilePolarity,Negative*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:48*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/production/gerbers/snips_controller-F_Paste.gbr b/PCB/production/gerbers/snips_controller-F_Paste.gbr
index 9bda026..fd7fe61 100644
--- a/PCB/production/gerbers/snips_controller-F_Paste.gbr
+++ b/PCB/production/gerbers/snips_controller-F_Paste.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:47-07:00*%
+%TF.CreationDate,2026-09-23T21:17:53-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Paste,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:47*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr b/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr
index 8d70acf..48f6c9c 100644
--- a/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr
+++ b/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:48-07:00*%
+%TF.CreationDate,2026-09-23T21:17:54-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Legend,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:48*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/production/gerbers/snips_controller-In1_Cu.gbr b/PCB/production/gerbers/snips_controller-In1_Cu.gbr
index 895803a..6e7ea18 100644
--- a/PCB/production/gerbers/snips_controller-In1_Cu.gbr
+++ b/PCB/production/gerbers/snips_controller-In1_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:47-07:00*%
+%TF.CreationDate,2026-09-23T21:17:53-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L2,Inr*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:47*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53*
 %MOMM*%
 %LPD*%
 G01*
@@ -174,6 +174,7 @@ X150160000Y-63000000D03*
 %TD*%
 D21*
 %TO.N,3V3*%
+X149550000Y-132950000D03*
 X139342332Y-122557668D03*
 X122500000Y-107500000D03*
 X127110000Y-120400000D03*
@@ -217,7 +218,6 @@ X139500000Y-118500000D03*
 X149800000Y-150800000D03*
 X134700000Y-119750000D03*
 X139500000Y-88000000D03*
-X149950000Y-134800000D03*
 X145000000Y-123500000D03*
 X145250000Y-65100000D03*
 X123500000Y-124000000D03*
@@ -254,11 +254,6 @@ X145000000Y-78500000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO6*%
 X148500000Y-90302943D03*
 X145000000Y-77000000D03*
-%TO.N,/Power_Buck/PWR_EN*%
-X149000000Y-112000000D03*
-X133588870Y-113975000D03*
-X143000000Y-114500000D03*
-X133850000Y-111000000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO3*%
 X145500000Y-80500000D03*
 X145000000Y-109500000D03*
@@ -333,6 +328,11 @@ X143600000Y-124150000D03*
 X136275000Y-108200000D03*
 X149350000Y-130760000D03*
 X139000000Y-119124499D03*
+%TO.N,/Power_Buck/PWR_EN*%
+X149000000Y-112000000D03*
+X133588870Y-113975000D03*
+X143000000Y-114500000D03*
+X133850000Y-111000000D03*
 %TD*%
 %TA.AperFunction,Conductor*%
 %TO.N,3V3*%
@@ -2287,67 +2287,6 @@ X127230264Y-139966498D01*
 X127230261Y-139966510D01*
 X127199500Y-140121153D01*
 X120250500Y-140121153D01*
-X120250500Y-134721153D01*
-X149149500Y-134721153D01*
-X149149500Y-134878846D01*
-X149180261Y-135033489D01*
-X149180264Y-135033501D01*
-X149240602Y-135179172D01*
-X149240609Y-135179185D01*
-X149328210Y-135310288D01*
-X149328213Y-135310292D01*
-X149439707Y-135421786D01*
-X149439711Y-135421789D01*
-X149570814Y-135509390D01*
-X149570827Y-135509397D01*
-X149716498Y-135569735D01*
-X149716503Y-135569737D01*
-X149871153Y-135600499D01*
-X149871156Y-135600500D01*
-X149871158Y-135600500D01*
-X150028844Y-135600500D01*
-X150028845Y-135600499D01*
-X150183497Y-135569737D01*
-X150329179Y-135509394D01*
-X150460289Y-135421789D01*
-X150571789Y-135310289D01*
-X150659394Y-135179179D01*
-X150719737Y-135033497D01*
-X150750500Y-134878842D01*
-X150750500Y-134721158D01*
-X150750500Y-134721155D01*
-X150750499Y-134721153D01*
-X150719738Y-134566510D01*
-X150719737Y-134566503D01*
-X150719735Y-134566498D01*
-X150659397Y-134420827D01*
-X150659390Y-134420814D01*
-X150571789Y-134289711D01*
-X150571786Y-134289707D01*
-X150460292Y-134178213D01*
-X150460288Y-134178210D01*
-X150329185Y-134090609D01*
-X150329172Y-134090602D01*
-X150183501Y-134030264D01*
-X150183489Y-134030261D01*
-X150028845Y-133999500D01*
-X150028842Y-133999500D01*
-X149871158Y-133999500D01*
-X149871155Y-133999500D01*
-X149716510Y-134030261D01*
-X149716498Y-134030264D01*
-X149570827Y-134090602D01*
-X149570814Y-134090609D01*
-X149439711Y-134178210D01*
-X149439707Y-134178213D01*
-X149328213Y-134289707D01*
-X149328210Y-134289711D01*
-X149240609Y-134420814D01*
-X149240602Y-134420827D01*
-X149180264Y-134566498D01*
-X149180261Y-134566510D01*
-X149149500Y-134721153D01*
-X120250500Y-134721153D01*
 X120250500Y-132405653D01*
 X122384000Y-132405653D01*
 X122384000Y-132563346D01*
diff --git a/PCB/production/gerbers/snips_controller-In2_Cu.gbr b/PCB/production/gerbers/snips_controller-In2_Cu.gbr
index ba03974..619a591 100644
--- a/PCB/production/gerbers/snips_controller-In2_Cu.gbr
+++ b/PCB/production/gerbers/snips_controller-In2_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:34:47-07:00*%
+%TF.CreationDate,2026-09-23T21:17:53-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L3,Inr*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:34:47*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53*
 %MOMM*%
 %LPD*%
 G01*
@@ -174,6 +174,7 @@ X150160000Y-63000000D03*
 %TD*%
 D21*
 %TO.N,3V3*%
+X149550000Y-132950000D03*
 X139342332Y-122557668D03*
 X122500000Y-107500000D03*
 X127110000Y-120400000D03*
@@ -217,7 +218,6 @@ X139500000Y-118500000D03*
 X149800000Y-150800000D03*
 X134700000Y-119750000D03*
 X139500000Y-88000000D03*
-X149950000Y-134800000D03*
 X145000000Y-123500000D03*
 X145250000Y-65100000D03*
 X123500000Y-124000000D03*
@@ -254,11 +254,6 @@ X145000000Y-78500000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO6*%
 X148500000Y-90302943D03*
 X145000000Y-77000000D03*
-%TO.N,/Power_Buck/PWR_EN*%
-X149000000Y-112000000D03*
-X133588870Y-113975000D03*
-X143000000Y-114500000D03*
-X133850000Y-111000000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO3*%
 X145500000Y-80500000D03*
 X145000000Y-109500000D03*
@@ -333,6 +328,11 @@ X143600000Y-124150000D03*
 X136275000Y-108200000D03*
 X149350000Y-130760000D03*
 X139000000Y-119124499D03*
+%TO.N,/Power_Buck/PWR_EN*%
+X149000000Y-112000000D03*
+X133588870Y-113975000D03*
+X143000000Y-114500000D03*
+X133850000Y-111000000D03*
 %TD*%
 %TA.AperFunction,Conductor*%
 %TO.N,GND*%
@@ -2201,15 +2201,75 @@ X123417997Y-133254237D01*
 X123563679Y-133193894D01*
 X123694789Y-133106289D01*
 X123806289Y-132994789D01*
+X123888900Y-132871153D01*
+X148749500Y-132871153D01*
+X148749500Y-133028846D01*
+X148780261Y-133183489D01*
+X148780264Y-133183501D01*
+X148840602Y-133329172D01*
+X148840609Y-133329185D01*
+X148928210Y-133460288D01*
+X148928213Y-133460292D01*
+X149039707Y-133571786D01*
+X149039711Y-133571789D01*
+X149170814Y-133659390D01*
+X149170827Y-133659397D01*
+X149316498Y-133719735D01*
+X149316503Y-133719737D01*
+X149471153Y-133750499D01*
+X149471156Y-133750500D01*
+X149471158Y-133750500D01*
+X149628844Y-133750500D01*
+X149628845Y-133750499D01*
+X149783497Y-133719737D01*
+X149929179Y-133659394D01*
+X150060289Y-133571789D01*
+X150171789Y-133460289D01*
+X150259394Y-133329179D01*
+X150319737Y-133183497D01*
+X150350500Y-133028842D01*
+X150350500Y-132871158D01*
+X150350500Y-132871155D01*
+X150350499Y-132871153D01*
+X150319737Y-132716503D01*
+X150319735Y-132716498D01*
+X150259397Y-132570827D01*
+X150259390Y-132570814D01*
+X150171789Y-132439711D01*
+X150171786Y-132439707D01*
+X150060292Y-132328213D01*
+X150060288Y-132328210D01*
+X149929185Y-132240609D01*
+X149929172Y-132240602D01*
+X149783501Y-132180264D01*
+X149783489Y-132180261D01*
+X149628845Y-132149500D01*
+X149628842Y-132149500D01*
+X149471158Y-132149500D01*
+X149471155Y-132149500D01*
+X149316510Y-132180261D01*
+X149316498Y-132180264D01*
+X149170827Y-132240602D01*
+X149170814Y-132240609D01*
+X149039711Y-132328210D01*
+X149039707Y-132328213D01*
+X148928213Y-132439707D01*
+X148928210Y-132439711D01*
+X148840609Y-132570814D01*
+X148840602Y-132570827D01*
+X148780264Y-132716498D01*
+X148780261Y-132716510D01*
+X148749500Y-132871153D01*
+X123888900Y-132871153D01*
 X123893894Y-132863679D01*
 X123954237Y-132717997D01*
 X123985000Y-132563342D01*
 X123985000Y-132405658D01*
 X123985000Y-132405655D01*
 X123984999Y-132405653D01*
-X123954238Y-132251010D01*
+X123969595Y-132328211D01*
 X123954237Y-132251003D01*
-X123954235Y-132250998D01*
+X123949932Y-132240609D01*
 X123893897Y-132105327D01*
 X123893890Y-132105314D01*
 X123806289Y-131974211D01*
diff --git a/PCB/production/gerbers/snips_controller-NPTH.drl b/PCB/production/gerbers/snips_controller-NPTH.drl
index 51db8db..f7586e5 100644
--- a/PCB/production/gerbers/snips_controller-NPTH.drl
+++ b/PCB/production/gerbers/snips_controller-NPTH.drl
@@ -1,7 +1,7 @@
 M48
-; DRILL file KiCad 10.0.5 date 2026-09-23T20:34:44
+; DRILL file KiCad 10.0.5 date 2026-09-23T21:17:50
 ; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-09-23T20:34:44-07:00
+; #@! TF.CreationDate,2026-09-23T21:17:50-07:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
 ; #@! TF.FileFunction,NonPlated,1,4,NPTH
 FMAT,2
diff --git a/PCB/production/gerbers/snips_controller-PTH.drl b/PCB/production/gerbers/snips_controller-PTH.drl
index 1ab4d8b..f0c99fd 100644
--- a/PCB/production/gerbers/snips_controller-PTH.drl
+++ b/PCB/production/gerbers/snips_controller-PTH.drl
@@ -1,7 +1,7 @@
 M48
-; DRILL file KiCad 10.0.5 date 2026-09-23T20:34:44
+; DRILL file KiCad 10.0.5 date 2026-09-23T21:17:50
 ; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-09-23T20:34:44-07:00
+; #@! TF.CreationDate,2026-09-23T21:17:50-07:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
 ; #@! TF.FileFunction,Plated,1,4,PTH
 FMAT,2
@@ -142,8 +142,8 @@ X148.0Y-91.5
 X148.5Y-90.303
 X149.0Y-112.0
 X149.35Y-130.76
+X149.55Y-132.95
 X149.8Y-150.8
-X149.95Y-134.8
 X150.3Y-77.5
 X150.5Y-90.5
 X150.5Y-100.5
diff --git a/PCB/production/gerbers/snips_controller-job.gbrjob b/PCB/production/gerbers/snips_controller-job.gbrjob
index e641e87..1bf2ebb 100644
--- a/PCB/production/gerbers/snips_controller-job.gbrjob
+++ b/PCB/production/gerbers/snips_controller-job.gbrjob
@@ -5,7 +5,7 @@
       "Application": "Pcbnew",
       "Version": "10.0.5"
     },
-    "CreationDate": "2026-09-23T20:34:48-07:00"
+    "CreationDate": "2026-09-23T21:17:54-07:00"
   },
   "GeneralSpecs": {
     "ProjectId": {
diff --git a/PCB/production/jlcpcb/Snips_1_1.zip b/PCB/production/jlcpcb/Snips_1_1.zip
index 9ceee39..9db07d2 100644
Binary files a/PCB/production/jlcpcb/Snips_1_1.zip and b/PCB/production/jlcpcb/Snips_1_1.zip differ
diff --git a/PCB/production/jlcpcb/netlist.ipc b/PCB/production/jlcpcb/netlist.ipc
index 7ef35ca..05e495e 100644
--- a/PCB/production/jlcpcb/netlist.ipc
+++ b/PCB/production/jlcpcb/netlist.ipc
@@ -1,6 +1,7 @@
 P  CODE 00
 P  UNITS CUST 0
 P  arrayDim   N
+3173V3              VIA        MD0118PA00X+058878Y-052343X0236Y0000R000S3
 3173V3              VIA        MD0118PA00X+054859Y-048251X0236Y0000R000S3
 3173V3              VIA        MD0118PA00X+048228Y-042323X0236Y0000R000S3
 3173V3              VIA        MD0118PA00X+050043Y-047402X0236Y0000R000S3
@@ -42,7 +43,6 @@ P  arrayDim   N
 317GND              VIA        MD0118PA00X+058976Y-059370X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+053031Y-047146X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+054921Y-034646X0236Y0000R000S3
-317GND              VIA        MD0118PA00X+059035Y-053071X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+057087Y-048622X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+057185Y-025630X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+048622Y-048819X0236Y0000R000S3
@@ -73,10 +73,6 @@ P  arrayDim   N
 317ECT/BTN_MACRO5   VIA        MD0118PA00X+057087Y-030906X0236Y0000R000S3
 317ECT/BTN_MACRO6   VIA        MD0118PA00X+058465Y-035552X0236Y0000R000S3
 317ECT/BTN_MACRO6   VIA        MD0118PA00X+057087Y-030315X0236Y0000R000S3
-317ER_BUCK/PWR_EN   VIA        MD0118PA00X+058661Y-044094X0236Y0000R000S3
-317ER_BUCK/PWR_EN   VIA        MD0118PA00X+052594Y-044872X0236Y0000R000S3
-317ER_BUCK/PWR_EN   VIA        MD0118PA00X+056299Y-045079X0236Y0000R000S3
-317ER_BUCK/PWR_EN   VIA        MD0118PA00X+052697Y-043701X0236Y0000R000S3
 317ECT/BTN_MACRO3   VIA        MD0118PA00X+057283Y-031693X0236Y0000R000S3
 317ECT/BTN_MACRO3   VIA        MD0118PA00X+057087Y-043110X0236Y0000R000S3
 317T/BTN_TRIG_DIG   VIA        MD0118PA00X+049905Y-030215X0236Y0000R000S3
@@ -128,6 +124,10 @@ P  arrayDim   N
 317VSYS             VIA        MD0118PA00X+053652Y-042598X0236Y0000R000S3
 317VSYS             VIA        MD0118PA00X+058799Y-051480X0236Y0000R000S3
 317VSYS             VIA        MD0118PA00X+054724Y-046899X0236Y0000R000S3
+317ER_BUCK/PWR_EN   VIA        MD0118PA00X+058661Y-044094X0236Y0000R000S3
+317ER_BUCK/PWR_EN   VIA        MD0118PA00X+052594Y-044872X0236Y0000R000S3
+317ER_BUCK/PWR_EN   VIA        MD0118PA00X+056299Y-045079X0236Y0000R000S3
+317ER_BUCK/PWR_EN   VIA        MD0118PA00X+052697Y-043701X0236Y0000R000S3
 3173V3              U_XBEE-1    D0362PA00X+055906Y-050197X0563Y0000R090S0
 317SH}DIO13-PAD2)   U_XBEE-2    D0362PA00X+055118Y-050197X0563Y0000R090S0
 317SH}DIO14-PAD3)   U_XBEE-3    D0362PA00X+054331Y-050197X0563Y0000R090S0
@@ -360,7 +360,7 @@ P  arrayDim   N
 327GND              C_3V3_-2          A01X+050118Y-026260X0220Y0244R270S2
 327_CORE/MCU_BOOT   R_BOOT-1          A01X+058465Y-032374X0213Y0252R090S2
 3273V3              R_BOOT-2          A01X+058465Y-032776X0213Y0252R090S2
-327VSYS             R_BTN_-1          A04X+058728Y-052638X0213Y0252R180S1
+3273V3              R_BTN_-1          A04X+058728Y-052638X0213Y0252R180S1
 327/PWR_BTN_SENSE   R_BTN_-2          A04X+058327Y-052638X0213Y0252R180S1
 327VSYS             C_SYS_-1          A04X+054331Y-046063X0394Y0571R000S1
 327GND              C_SYS_-2          A04X+055079Y-046063X0394Y0571R000S1
diff --git a/PCB/production/placement/snips_controller-pnp_bottom.gbr b/PCB/production/placement/snips_controller-pnp_bottom.gbr
index 2d3ee5a..32bb045 100644
--- a/PCB/production/placement/snips_controller-pnp_bottom.gbr
+++ b/PCB/production/placement/snips_controller-pnp_bottom.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:35:13-07:00*%
+%TF.CreationDate,2026-09-23T21:18:22-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Component,L4,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:35:13*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:18:22*
 %MOMM*%
 %LPD*%
 G01*
@@ -418,7 +418,7 @@ X147500000Y-114500000D03*
 D10*
 %TO.C,Q_LATCH1*%
 %TO.CFtp,SOT-23*%
-%TO.CVal,2N7002*%
+%TO.CVal,AO3400A*%
 %TO.CLbN,Package_TO_SOT_SMD*%
 %TO.CMnt,SMD*%
 %TO.CRot,180*%
diff --git a/PCB/production/placement/snips_controller-pnp_top.gbr b/PCB/production/placement/snips_controller-pnp_top.gbr
index fb117c2..9e8ed78 100644
--- a/PCB/production/placement/snips_controller-pnp_top.gbr
+++ b/PCB/production/placement/snips_controller-pnp_top.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-09-23T20:35:13-07:00*%
+%TF.CreationDate,2026-09-23T21:18:22-07:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Component,L1,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 20:35:13*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:18:22*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/snips_controller.kicad_pcb b/PCB/snips_controller.kicad_pcb
index cd442a1..ea9daf7 100644
--- a/PCB/snips_controller.kicad_pcb
+++ b/PCB/snips_controller.kicad_pcb
@@ -14576,7 +14576,7 @@
 			(size 0.54 0.64)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net "VSYS")
+			(net "3V3")
 			(pintype "passive")
 			(uuid "c6d55744-4f81-474b-9493-5496c662a32a")
 		)
@@ -19795,7 +19795,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Value" "2N7002"
+		(property "Value" "AO3400A"
 			(at 0 -2.4 0)
 			(layer "B.Fab")
 			(uuid "4b9234fe-8e61-4982-93b5-7898f69b1ba1")
@@ -19831,7 +19831,7 @@
 				(justify mirror)
 			)
 		)
-		(property "MF" "Jiangsu Changjing Electronics Technology Co., Ltd."
+		(property "MF" "Alpha & Omega Semicon"
 			(at 0 0 0)
 			(unlocked yes)
 			(layer "B.Fab")
@@ -19845,7 +19845,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Manufacturer_Part_Number" "2N7002"
+		(property "Manufacturer_Part_Number" "AO3400A"
 			(at 0 0 0)
 			(unlocked yes)
 			(layer "B.Fab")
@@ -19859,7 +19859,7 @@
 				(justify mirror)
 			)
 		)
-		(property "LCSC" "C8545"
+		(property "LCSC" "C20917"
 			(at 0 0 0)
 			(unlocked yes)
 			(layer "B.Fab")
@@ -26796,6 +26796,14 @@
 		(net "3V3")
 		(uuid "6c4a90bf-abe8-4478-82c1-e78b76593884")
 	)
+	(via
+		(at 149.55 132.95)
+		(size 0.6)
+		(drill 0.3)
+		(layers "F.Cu" "B.Cu")
+		(net "3V3")
+		(uuid "8879adcf-b8ca-4039-8b29-c975c4e60977")
+	)
 	(via
 		(at 148 91.5)
 		(size 0.6)
@@ -26860,6 +26868,22 @@
 		(net "3V3")
 		(uuid "02472945-4724-4625-98ae-dba7de52cad7")
 	)
+	(segment
+		(start 149.17 133.33)
+		(end 149.55 132.95)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "3V3")
+		(uuid "055bcd30-3e42-4d45-90c3-77946fa3f5ab")
+	)
+	(segment
+		(start 149.17 133.7)
+		(end 149.17 133.33)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "3V3")
+		(uuid "0b3f9474-413e-44ed-8674-763f75d90228")
+	)
 	(segment
 		(start 122.025 109.05)
 		(end 122.025 107.975)
@@ -28316,14 +28340,6 @@
 		(net "GND")
 		(uuid "ad1c518d-9783-4597-a789-155e9d6edb5d")
 	)
-	(via
-		(at 149.95 134.8)
-		(size 0.6)
-		(drill 0.3)
-		(layers "F.Cu" "B.Cu")
-		(net "GND")
-		(uuid "b16b986f-adf1-49fa-a375-9c1e2966cf84")
-	)
 	(via
 		(at 145 123.5)
 		(size 0.6)
@@ -28780,14 +28796,6 @@
 		(net "GND")
 		(uuid "cb13d6ac-c05a-401f-9e12-33663764d2e5")
 	)
-	(segment
-		(start 149.9 134.85)
-		(end 149.95 134.8)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "GND")
-		(uuid "cc4ae41a-e69b-4d6c-aa14-a35f608fe145")
-	)
 	(segment
 		(start 133.45 120.070634)
 		(end 133.020634 120.5)
@@ -33564,6 +33572,14 @@
 		(net "/MCU_Core/PWR_BTN_SENSE")
 		(uuid "e20931ac-02c3-466b-9462-1b96ab4e61db")
 	)
+	(segment
+		(start 154.4 129.2)
+		(end 150.6 133)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_BTN_SENSE")
+		(uuid "00ac842d-27ce-4f0b-8beb-c7be2481c9b2")
+	)
 	(segment
 		(start 145.98 137.5)
 		(end 136.48 147)
@@ -33572,6 +33588,14 @@
 		(net "/MCU_Core/PWR_BTN_SENSE")
 		(uuid "0c3c3408-8213-442c-88b2-b370121f13e0")
 	)
+	(segment
+		(start 150.6 133)
+		(end 150.6 133.8)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_BTN_SENSE")
+		(uuid "1232b164-e698-4434-8f64-28e78d113c05")
+	)
 	(segment
 		(start 147.84 135.64)
 		(end 147.84 135.15)
@@ -33581,12 +33605,12 @@
 		(uuid "1261674a-a7e0-4909-8405-c69c427b2185")
 	)
 	(segment
-		(start 150.6 133)
-		(end 150.6 135.8)
+		(start 148.54 134.45)
+		(end 148.14 134.85)
 		(width 0.2)
 		(layer "B.Cu")
 		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "39442486-2a41-49ca-b06b-3d04642327c5")
+		(uuid "16c38f20-84fd-4adf-a424-d9cbbef222b1")
 	)
 	(segment
 		(start 147.84 135.64)
@@ -33596,14 +33620,6 @@
 		(net "/MCU_Core/PWR_BTN_SENSE")
 		(uuid "3e00537c-b089-4f84-810c-25413f57b4c3")
 	)
-	(segment
-		(start 154.4 129.2)
-		(end 154.4 81.4)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "44b7339f-66b5-4ad6-8844-6ff268e42bfc")
-	)
 	(segment
 		(start 147.1 133.7)
 		(end 146.1 132.7)
@@ -33621,12 +33637,12 @@
 		(uuid "4688f583-b875-4685-9b2c-da1b8b84f151")
 	)
 	(segment
-		(start 150.6 133)
-		(end 154.4 129.2)
+		(start 150.6 133.8)
+		(end 149.95 134.45)
 		(width 0.2)
 		(layer "B.Cu")
 		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "47b01ca0-6dc1-4a53-829d-d5ba71f96892")
+		(uuid "569465fe-152d-42ea-8365-bc12eabfd686")
 	)
 	(segment
 		(start 148.14 134.85)
@@ -33637,36 +33653,36 @@
 		(uuid "65b875e1-6810-47e1-9bf0-cbdc16aad1df")
 	)
 	(segment
-		(start 154.4 81.4)
-		(end 154.1 81.1)
+		(start 147.84 135.15)
+		(end 148.14 134.85)
 		(width 0.2)
 		(layer "B.Cu")
 		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "6ef58e32-ed1b-4559-a754-e8206743f051")
+		(uuid "77d28662-7d06-4967-9e41-f9dcb72e1920")
 	)
 	(segment
-		(start 147.84 135.15)
-		(end 148.14 134.85)
+		(start 154.1 81.1)
+		(end 154.4 81.4)
 		(width 0.2)
 		(layer "B.Cu")
 		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "77d28662-7d06-4967-9e41-f9dcb72e1920")
+		(uuid "7f5306c8-14c5-4bfb-9dc7-347b80634ddc")
 	)
 	(segment
-		(start 148.15 133.7)
-		(end 147.1 133.7)
+		(start 149.95 134.45)
+		(end 148.54 134.45)
 		(width 0.2)
 		(layer "B.Cu")
 		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "968994fa-9448-43ba-9aa4-f60b4f1c9273")
+		(uuid "8d396879-0032-49c6-a7f4-16ab785a87ab")
 	)
 	(segment
-		(start 150 136.4)
-		(end 149.69 136.4)
+		(start 148.15 133.7)
+		(end 147.1 133.7)
 		(width 0.2)
 		(layer "B.Cu")
 		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "96b7df13-9478-4c63-af4d-249b6e84aa8a")
+		(uuid "968994fa-9448-43ba-9aa4-f60b4f1c9273")
 	)
 	(segment
 		(start 125.063866 147)
@@ -33676,6 +33692,14 @@
 		(net "/MCU_Core/PWR_BTN_SENSE")
 		(uuid "9e2a79f8-c5c3-4493-b9fb-6f9e94d2f410")
 	)
+	(segment
+		(start 154.4 81.4)
+		(end 154.4 129.2)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_BTN_SENSE")
+		(uuid "a069970d-c8d2-4f92-a9a9-cc8882cf4960")
+	)
 	(segment
 		(start 148.14 133.71)
 		(end 148.15 133.7)
@@ -33692,22 +33716,6 @@
 		(net "/MCU_Core/PWR_BTN_SENSE")
 		(uuid "c39c5559-88a9-47b7-9f8d-fe71d6b42ab7")
 	)
-	(segment
-		(start 150.6 135.8)
-		(end 150 136.4)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "e1b928d8-91bd-44f6-b531-45df37d48b83")
-	)
-	(segment
-		(start 149.69 136.4)
-		(end 148.14 134.85)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_BTN_SENSE")
-		(uuid "eb794cb7-30f2-4636-a7c8-2b6393224ff0")
-	)
 	(segment
 		(start 136.48 147)
 		(end 125.063866 147)
@@ -34540,14 +34548,6 @@
 		(net "VSYS")
 		(uuid "2fcdfb45-544d-4d11-b3d5-a824922c76f3")
 	)
-	(segment
-		(start 150.25 132.62)
-		(end 149.17 133.7)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "VSYS")
-		(uuid "33d45676-f27b-412f-bd56-d35f5b27c595")
-	)
 	(segment
 		(start 149.35 130.76)
 		(end 150.25 131.66)
@@ -34756,14 +34756,6 @@
 		(net "VSYS")
 		(uuid "f9483ef8-9b26-4542-bdb5-115572e2cee3")
 	)
-	(segment
-		(start 150.25 131.66)
-		(end 150.25 132.62)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "VSYS")
-		(uuid "fc3e8858-9f50-43d1-880f-f05010ef1922")
-	)
 	(segment
 		(start 147.5 116.825)
 		(end 148.625 117.95)
@@ -36127,71 +36119,56 @@
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-				(xy 120.2505 134.721153) (xy 149.1495 134.721153) (xy 149.1495 134.878846) (xy 149.180261 135.033489)
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diff --git a/PCB/snips_controller.kicad_pcb.zip b/PCB/snips_controller.kicad_pcb.zip
index 04b0a51..215a17d 100644
Binary files a/PCB/snips_controller.kicad_pcb.zip and b/PCB/snips_controller.kicad_pcb.zip differ