diff --git a/PCB/diagrams/power_control_layout.html b/PCB/diagrams/power_control_layout.html index 478cdc5..f77ef52 100644 --- a/PCB/diagrams/power_control_layout.html +++ b/PCB/diagrams/power_control_layout.html @@ -280,6 +280,7 @@

What's on this sheet

D_OR1 / D_OR21N4148WSOD-123Diode-OR: PWR_BTN_TRIGGER (actual button press, via the inverter) or MCU hold, either one latches power on R_GATE1100kΩ0402Q_PWR1 gate pull-up — off by default R_LATCH_G11MΩ0402Q_LATCH1 gate pull-down — off by default; sized to not starve the diode-OR's drive (callout D) + C_LATCH_G1100nF0402Latch-gate filter — keeps the ~2ms battery-insertion transient from lifting PWR_LATCH_G (callout I) R_BTN_PU1100kΩ0402Button sense pull-up to 3V3 (not VSYS) — MCU reads pressed (0V) vs idle (3.3V); callout H R_INV_BASE1100kΩ0402Dedicated VSYS pull-up for Q_INV1's base — decoupled from PWR_BTN_SENSE (callout F) D_INV_ISO1BAT54WSOD-123Schottky isolator: lets a press pull Q_INV1's base low without loading PWR_BTN_SENSE @@ -406,6 +407,14 @@

Suggested floorplan

R_LATCH_G1 1M + + + + + + C_LATCH_G1 100n + D_OR1 (from inverter) @@ -509,6 +518,10 @@

Suggested floorplan

G + + + + I @@ -534,6 +547,7 @@

Why it's arranged this way

  • F

    D_OR1 can't read PWR_BTN_SENSE directly — found the hard way, on real hardware. The original design had R_BTN_PU1 (to VSYS) and a since-removed R_PWR_SENSE1 (to GND) both on that node, dividing it to roughly half VSYS at idle — comfortably above a diode's ~0.6V forward threshold, so D_OR1 was forward-biased (and the board powered on) the instant a battery was plugged in, button or no button. The inverter fixes this properly instead of just retuning the divider: idle, Q_INV1 is on and holds PWR_BTN_TRIGGER at GND; pressed, it turns off and R_INV_PU1 pulls PWR_BTN_TRIGGER to VSYS. Only a real press can forward-bias D_OR1 now. Keep this block close to D_OR1 — it's parts serving one signal, not worth spreading out.

    Second-order bug, found the same way: the inverter's own base resistor originally tapped PWR_BTN_SENSE directly, in series with R_BTN_PU1 — stealing enough idle base current to sag the MCU's own button-read node to ~1V instead of near-VSYS. R_INV_BASE1 is now its own dedicated 100kΩ pull-up straight to VSYS (not sharing current with R_BTN_PU1), and D_INV_ISO1 (a Schottky, chosen specifically for its lower forward drop than Q_INV1's own base-emitter junction) lets a press still pull the base low without ever loading PWR_BTN_SENSE.

  • G

    PWR_EN had no defined rest state — TI's own datasheet says not to do this. Q_PWR1's drain feeds the buck's EN pin directly, with nothing else on that node. TLV62569's EN pin is a bare comparator input with no internal pull ("Do not leave floating" per its datasheet) — with Q_PWR1 off, EN was held by MOSFET/input leakage alone, no guaranteed logic level. R_PWR_EN_PD1 (100kΩ to GND) fixes it: negligible loading when Q_PWR1's tens-of-mΩ RDS(on) is driving EN high, solid GND the instant it's off.

  • H

    PWR_BTN_SENSE must never sit above the MCU's rail. It lands directly on GPIO2 (pin 38), whose ceiling is VDD + 0.3V (~3.6V), but R_BTN_PU1 used to pull it to VSYS — up to ~4.5V on USB, and it back-fed the unpowered 3V3 rail through the pin's clamp diode whenever the MCU was off. Since R_INV_BASE1 gave the inverter its own VSYS pull-up (callout F), R_BTN_PU1 no longer has to supply the inverter, so it now pulls to 3V3: idle reads 3.3V, and with the MCU off the node is simply unpowered instead of leaking into the rail.

    • +
  • I

    Battery insertion used to blip PWR_EN for ~2ms — found in simulation, since no board existed to bench-test. When VSYS first appears, Q_INV1 isn't conducting yet: its base current is diverted through D_INV_ISO1 into the discharged C_DBNC1 until that charges to ~0.4V. For that ~1–2ms PWR_BTN_TRIGGER follows VSYS, PWR_LATCH_G rises to ~VSYS−0.6V, and Q_PWR1 briefly enables the buck. C_LATCH_G1 (100nF against the 100kΩ pull-up) makes the gate rise slowly enough that the transient peaks at ~0.3V — well under the AO3400A's minimum threshold — at the cost of 4–8ms of press latency, and it gives release a little extra hold time. Keep it right at PWR_LATCH_G.

    • @@ -548,6 +562,7 @@

    Routing priority

  • Keep R_INV_BASE1, D_INV_ISO1, Q_INV1, and R_INV_PU1 together as their own small block, close to D_OR1 — they're a single-purpose inverter, not independent parts.
  • Bring PWR_BTN_SENSE and PWR_HOLD in from wherever the MCU sheet actually sits — these are off-sheet nets, not local components.
  • Drop R_PWR_EN_PD1 right at Q_PWR1's drain, on the way to PWR_EN leaving the sheet — it's a bias resistor for that pin, not an independent part.
    • +
  • Put C_LATCH_G1 on the PWR_LATCH_G node next to R_LATCH_G1 and Q_LATCH1's gate, with a short GND return.
    • diff --git a/PCB/diagrams/power_control_layout.md b/PCB/diagrams/power_control_layout.md index 2527503..0ef1a7e 100644 --- a/PCB/diagrams/power_control_layout.md +++ b/PCB/diagrams/power_control_layout.md @@ -18,6 +18,7 @@ A press-to-start, software-held latch: the button turns the board on, the MCU ha | D_OR1 / D_OR2 | 1N4148W | SOD-123 | Diode-OR: `PWR_BTN_TRIGGER` (actual button press, via the inverter) or MCU hold, either one latches power on | | R_GATE1 | 100kΩ | 0402 | Q_PWR1 gate pull-up — off by default | | R_LATCH_G1 | 1MΩ | 0402 | Q_LATCH1 gate pull-down — off by default; sized to not starve the diode-OR's drive (callout D) | +| C_LATCH_G1 | 100nF | 0402 | Latch-gate filter — keeps the ~2ms battery-insertion transient from lifting `PWR_LATCH_G` (callout I) | | R_BTN_PU1 | 100kΩ | 0402 | Button sense pull-up to **3V3** (not VSYS) — MCU reads pressed (0V) vs idle (3.3V); callout H | | R_INV_BASE1 | 100kΩ | 0402 | Dedicated VSYS pull-up for Q_INV1's base — decoupled from `PWR_BTN_SENSE` (callout F) | | D_INV_ISO1 | BAT54W | SOD-123 | Schottky isolator: lets a press pull Q_INV1's base low without loading `PWR_BTN_SENSE` | @@ -50,6 +51,7 @@ Top copper layer. The VSYS→PWR_EN path runs straight across the top as one thi | **F** | **D_OR1 can't read `PWR_BTN_SENSE` directly — found the hard way, on real hardware.** The original design had `R_BTN_PU1` (to VSYS) and a since-removed `R_PWR_SENSE1` (to GND) both on that node, dividing it to roughly half VSYS at idle — comfortably above a diode's ~0.6V forward threshold, so `D_OR1` was forward-biased (and the board powered on) the instant a battery was plugged in, button or no button. The inverter fixes this properly instead of just retuning the divider: idle, `Q_INV1` is on and holds `PWR_BTN_TRIGGER` at GND; pressed, it turns off and `R_INV_PU1` pulls `PWR_BTN_TRIGGER` to VSYS. Only a real press can forward-bias `D_OR1` now. Keep this block close to `D_OR1` — it's parts serving one signal, not worth spreading out.

    **Second-order bug, found the same way:** the inverter's own base resistor originally tapped `PWR_BTN_SENSE` directly, in series with `R_BTN_PU1` — stealing enough idle base current to sag the MCU's own button-read node to ~1V instead of near-VSYS. `R_INV_BASE1` is now its own dedicated 100kΩ pull-up straight to VSYS (not sharing current with `R_BTN_PU1`), and `D_INV_ISO1` (a Schottky, chosen specifically for its lower forward drop than Q_INV1's own base-emitter junction) lets a press still pull the base low without ever loading `PWR_BTN_SENSE`. | | **G** | **`PWR_EN` had no defined rest state — TI's own datasheet says not to do this.** `Q_PWR1`'s drain feeds the buck's EN pin directly, with nothing else on that node. TLV62569's EN pin is a bare comparator input with no internal pull ("Do not leave floating" per its datasheet) — with `Q_PWR1` off, EN was held by MOSFET/input leakage alone, no guaranteed logic level. `R_PWR_EN_PD1` (100kΩ to GND) fixes it: negligible loading when `Q_PWR1`'s tens-of-mΩ RDS(on) is driving EN high, solid GND the instant it's off. | | **H** | **`PWR_BTN_SENSE` must never sit above the MCU's rail.** It lands directly on GPIO2 (pin 38), whose ceiling is VDD + 0.3V (~3.6V), but `R_BTN_PU1` used to pull it to VSYS — up to ~4.5V on USB, and it back-fed the unpowered 3V3 rail through the pin's clamp diode whenever the MCU was off. Since `R_INV_BASE1` gave the inverter its own VSYS pull-up (callout F), `R_BTN_PU1` no longer has to supply the inverter, so it now pulls to 3V3: idle reads 3.3V, and with the MCU off the node is simply unpowered instead of leaking into the rail. | +| **I** | **Battery insertion used to blip `PWR_EN` for ~2ms — found in simulation, since no board existed to bench-test.** When VSYS first appears, `Q_INV1` isn't conducting yet: its base current is diverted through `D_INV_ISO1` into the discharged `C_DBNC1` until that charges to ~0.4V. For that ~1–2ms `PWR_BTN_TRIGGER` follows VSYS, `PWR_LATCH_G` rises to ~VSYS−0.6V, and `Q_PWR1` briefly enables the buck. `C_LATCH_G1` (100nF against the 100kΩ pull-up) makes the gate rise slowly enough that the transient peaks at ~0.3V — well under the AO3400A's minimum threshold — at the cost of 4–8ms of press latency, and it gives release a little extra hold time. Keep it right at `PWR_LATCH_G`. | ## Routing priority @@ -62,6 +64,7 @@ The button's position is fixed by the enclosure before you start — everything 5. Keep R_INV_BASE1, D_INV_ISO1, Q_INV1, and R_INV_PU1 together as their own small block, close to D_OR1 — they're a single-purpose inverter, not independent parts. 6. Bring PWR_BTN_SENSE and PWR_HOLD in from wherever the MCU sheet actually sits — these are off-sheet nets, not local components. 7. Drop `R_PWR_EN_PD1` right at Q_PWR1's drain, on the way to `PWR_EN` leaving the sheet — it's a bias resistor for that pin, not an independent part. +8. Put `C_LATCH_G1` on the `PWR_LATCH_G` node next to `R_LATCH_G1` and `Q_LATCH1`'s gate, with a short GND return. > **Checked, not just assumed:** DMG2305UX is rated for ~4A continuous with 35–50mΩ RDS(on) in this SOT-23 package — comfortably oversized for a handheld controller's sub-2A system budget, so this isn't a thermal risk the way the charger's WSON is. MMBT3904 is a general-purpose small-signal part switching microamps here (just enough to bias a diode) — nowhere near its ratings, no thermal consideration needed. BAT54W's job is purely to isolate two nodes at sub-1V forward drop, also nowhere near its ratings. Connectivity alone (ERC, netlist, DRC) doesn't catch bad DC bias points — the `R_LATCH_G1`/`PWR_BTN_SENSE` loading bugs in callouts D and F, and the floating `PWR_EN` in callout G, all passed every connectivity check and were only found by actually working through the bias/divider math or reading the driven IC's own datasheet, so don't treat a clean ERC/DRC as proof a gate-drive, sense, or enable network will behave. diff --git a/PCB/diagrams/power_control_layout.svg b/PCB/diagrams/power_control_layout.svg index 0e11f05..f2e38ad 100644 --- a/PCB/diagrams/power_control_layout.svg +++ b/PCB/diagrams/power_control_layout.svg @@ -106,6 +106,14 @@ R_LATCH_G1 1M + + + + + + C_LATCH_G1 100n + D_OR1 (from inverter) @@ -209,5 +217,9 @@ G + + + + I diff --git a/PCB/power_control.kicad_sch b/PCB/power_control.kicad_sch index e1852fa..da9e526 100644 --- a/PCB/power_control.kicad_sch +++ b/PCB/power_control.kicad_sch @@ -3204,6 +3204,151 @@ ) ) ) + (global_label "GND" + (shape passive) + (at 115.57 72.39 90) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "55f99604-9512-46a1-a9e2-2115e48ce76a") + (property "Intersheetrefs" "${INTERSHEET_REFS}" + (at 115.57 72.39 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (label "PWR_LATCH_G" + (at 115.57 80.01 270) + (effects + (font + (size 1.27 1.27) + ) + (justify right) + ) + (uuid "dd2dda05-27ed-472e-839c-3bb9502a566d") + ) + (symbol + (lib_id "Device:C") + (at 115.57 76.2 0) + (unit 1) + (body_style 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (in_pos_files yes) + (dnp no) + (fields_autoplaced yes) + (uuid "526a9667-117d-48b5-85bd-c2e58526ea56") + (property "Reference" "C_LATCH_G1" + (at 116.205 78.74 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "100nF" + (at 116.205 73.66 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0402_1005Metric" + (at 116.5352 72.39 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 115.57 76.2 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 115.57 76.2 0) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "MF" "Samsung Electro-Mechanics" + (at 0 0 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Manufacturer_Part_Number" "CL05B104KO5NNNC" + (at 0 0 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "LCSC" "C1525" + (at 0 0 0) + (hide yes) + (show_name no) + (do_not_autoplace no) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (pin "1" + (uuid "809a995a-f135-461e-8f70-899f7c158157") + ) + (pin "2" + (uuid "c3b11b9a-8585-42ac-a4c0-449d3e07d234") + ) + (instances + (project "snips_controller" + (path "/21935953-32a0-46ad-8079-8177920c6978/081a4841-1e21-4908-a8a8-37f54f8809f6" + (reference "C_LATCH_G1") + (unit 1) + ) + ) + ) + ) (symbol (lib_id "Device:D_Small") (at 63.5 76.2 0) diff --git a/PCB/production/bom/snips_controller-bom.csv b/PCB/production/bom/snips_controller-bom.csv index 63bda09..f07eace 100644 --- a/PCB/production/bom/snips_controller-bom.csv +++ b/PCB/production/bom/snips_controller-bom.csv @@ -1,7 +1,7 @@ "Id";"Designator";"Footprint";"Quantity";"Designation";"Supplier and ref"; 1;"BT1";"JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal";1;"JST-PH_2Pin_Battery_RightAngle_Horizontal";;; 2;"C_3V3_1, C_XBEE_VCC4";"C_0603_1608Metric";2;"10µF";;; -3;"C_3V3_2, C_DBNC1, C_HALL1, C_OLED_2, C_RGB1, C_STICK1, C_SYS_2, C_VIN_2, C_XBEE_RC1, C_XBEE_VCC1";"C_0402_1005Metric";10;"100nF";;; +3;"C_3V3_2, C_DBNC1, C_HALL1, C_LATCH_G1, C_OLED_2, C_RGB1, C_STICK1, C_SYS_2, C_VIN_2, C_XBEE_RC1, C_XBEE_VCC1";"C_0402_1005Metric";11;"100nF";;; 4;"C_3V3_3";"C_0402_1005Metric";1;"39pF";;; 5;"C_ACCEL_1";"C_0402_1005Metric";1;"10nF";;; 6;"C_ACCEL_2";"C_0402_1005Metric";1;"100pF";;; diff --git a/PCB/production/gerbers/snips_controller-B_Cu.gbr b/PCB/production/gerbers/snips_controller-B_Cu.gbr index 6f77dca..0d70ce0 100644 --- a/PCB/production/gerbers/snips_controller-B_Cu.gbr +++ b/PCB/production/gerbers/snips_controller-B_Cu.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:53-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Copper,L4,Bot*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* @@ -38,44 +38,44 @@ G04 Aperture macros list* -0.452743,0.716581,-0.451743,0.719581,-0.451472,0.720236,-0.450630,0.721920,-0.449743,0.724581,-0.448536,0.726536,-0.447108,0.727964,-0.446472,0.729236,-0.445536,0.730536,-0.444108,0.731964,-0.443472,0.733236,-0.442536,0.734536,-0.434536,0.742536,-0.433236,0.743472,-0.431964,0.744108,-0.430536,0.745536,-0.429236,0.746472,-0.427964,0.747108,-0.426536,0.748536,-0.424581,0.749743, -0.421920,0.750630,-0.420236,0.751472,-0.419581,0.751743,-0.416581,0.752743,-0.415000,0.753000,-0.413810,0.753000,-0.411581,0.753743,-0.410000,0.754000,-0.408810,0.754000,-0.406581,0.754743,-0.405000,0.755000,0.405000,0.755000,0.406581,0.754743,0.406581,0.754743,$1*% G04 Aperture macros list end* +%TA.AperFunction,SMDPad,CuDef*% +%ADD10RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*% +%TD*% %TA.AperFunction,ComponentPad*% -%ADD10C,1.431000*% +%ADD11C,1.431000*% %TD*% %TA.AperFunction,ComponentPad*% -%ADD11O,1.000000X2.100000*% +%ADD12O,1.000000X2.100000*% %TD*% %TA.AperFunction,ComponentPad*% -%ADD12O,1.000000X1.600000*% +%ADD13O,1.000000X1.600000*% %TD*% %TA.AperFunction,ComponentPad*% -%ADD13C,2.550000*% +%ADD14C,2.550000*% %TD*% %TA.AperFunction,ComponentPad*% -%ADD14C,2.050000*% +%ADD15C,2.050000*% %TD*% %TA.AperFunction,ComponentPad*% -%ADD15C,2.250000*% +%ADD16C,2.250000*% %TD*% %TA.AperFunction,SMDPad,CuDef*% -%ADD16RoundRect,0.135000X0.135000X0.185000X-0.135000X0.185000X-0.135000X-0.185000X0.135000X-0.185000X0*% +%ADD17RoundRect,0.135000X0.135000X0.185000X-0.135000X0.185000X-0.135000X-0.185000X0.135000X-0.185000X0*% %TD*% %TA.AperFunction,SMDPad,CuDef*% -%ADD17RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% +%ADD18RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% %TD*% %TA.AperFunction,SMDPad,CuDef*% -%ADD18RoundRect,0.150000X-0.587500X-0.150000X0.587500X-0.150000X0.587500X0.150000X-0.587500X0.150000X0*% +%ADD19RoundRect,0.150000X-0.587500X-0.150000X0.587500X-0.150000X0.587500X0.150000X-0.587500X0.150000X0*% %TD*% %TA.AperFunction,SMDPad,CuDef*% -%ADD19RoundRect,0.112500X-0.112500X0.187500X-0.112500X-0.187500X0.112500X-0.187500X0.112500X0.187500X0*% +%ADD20RoundRect,0.112500X-0.112500X0.187500X-0.112500X-0.187500X0.112500X-0.187500X0.112500X0.187500X0*% %TD*% %TA.AperFunction,ComponentPad*% -%ADD20RoundRect,0.250000X0.350000X0.625000X-0.350000X0.625000X-0.350000X-0.625000X0.350000X-0.625000X0*% +%ADD21RoundRect,0.250000X0.350000X0.625000X-0.350000X0.625000X-0.350000X-0.625000X0.350000X-0.625000X0*% %TD*% %TA.AperFunction,ComponentPad*% -%ADD21O,1.200000X1.750000*% -%TD*% -%TA.AperFunction,SMDPad,CuDef*% -%ADD22RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*% +%ADD22O,1.200000X1.750000*% %TD*% %TA.AperFunction,SMDPad,CuDef*% %ADD23RoundRect,0.250000X0.250000X0.475000X-0.250000X0.475000X-0.250000X-0.475000X0.250000X-0.475000X0*% @@ -148,6 +148,14 @@ G04 Aperture macros list end* %TD*% G04 APERTURE END LIST* D10* +%TO.P,C_LATCH_G1,1*% +%TO.N,GND*% +X146450000Y-119800000D03* +%TO.P,C_LATCH_G1,2*% +%TO.N,/Power_Control/PWR_LATCH_G*% +X146450000Y-120760000D03* +%TD*% +D11* %TO.P,U_XBEE1,1,VCC_1*% %TO.N,3V3*% X142000000Y-127500000D03* @@ -209,25 +217,25 @@ X140000000Y-149500000D03* %TO.N,unconnected-(U_XBEE1-AD0_{slash}DIO0-Pad20)*% X142000000Y-149500000D03* %TD*% -D11* +D12* %TO.P,J_USB1,SH,SHIELD_SH*% %TO.N,GND*% X133180000Y-153970000D03* -D12* +D13* X133180000Y-158150000D03* -D11* -X141820000Y-153970000D03* D12* +X141820000Y-153970000D03* +D13* X141820000Y-158150000D03* %TD*% -D13* +D14* %TO.P,J_STICK1,*% %TO.N,*% X131175000Y-90250000D03* X131175000Y-100250000D03* X143825000Y-90250000D03* X143825000Y-100250000D03* -D14* +D15* %TO.P,J_STICK1,1,X_LO_1*% %TO.N,GND*% X140000000Y-86520000D03* @@ -244,7 +252,7 @@ X146230000Y-95250000D03* X135000000Y-86520000D03* %TO.P,J_STICK1,3',Y_HI_3'*% X146230000Y-92750000D03* -D15* +D16* %TO.P,J_STICK1,a,SW_A_a*% %TO.N,/MCU_Core/BTN_STICK*% X134250000Y-101000000D03* @@ -258,7 +266,7 @@ X134250000Y-105500000D03* %TO.N,N/C*% X140750000Y-105500000D03* %TD*% -D16* +D17* %TO.P,R_BTN_PU1,1*% %TO.N,3V3*% X149170000Y-133700000D03* @@ -266,7 +274,7 @@ X149170000Y-133700000D03* %TO.N,/MCU_Core/PWR_BTN_SENSE*% X148150000Y-133700000D03* %TD*% -D17* +D18* %TO.P,C_SYS_1,1*% %TO.N,VSYS*% X138000000Y-117000000D03* @@ -274,7 +282,7 @@ X138000000Y-117000000D03* %TO.N,GND*% X139900000Y-117000000D03* %TD*% -D18* +D19* %TO.P,Q_PWR1,1,G_1*% %TO.N,/Power_Control/PWR_GATE*% X148625000Y-117950000D03* @@ -285,7 +293,7 @@ X148625000Y-116050000D03* %TO.N,/Power_Buck/PWR_EN*% X150500000Y-117000000D03* %TD*% -D19* +D20* %TO.P,D_VBUS_TVS1,1,A1_1*% %TO.N,VBUS*% X137400000Y-155150000D03* @@ -293,16 +301,16 @@ X137400000Y-155150000D03* %TO.N,GND*% X137400000Y-157250000D03* %TD*% -D20* +D21* %TO.P,BT1,1,Pin_1_1*% %TO.N,VBAT*% X152500000Y-68900000D03* -D21* +D22* %TO.P,BT1,2,Pin_2_2*% %TO.N,GND*% X150500000Y-68900000D03* %TD*% -D22* +D10* %TO.P,C_VIN_2,1*% %TO.N,VBUS*% X130000000Y-118040000D03* @@ -418,7 +426,7 @@ X150250000Y-131660000D03* %TO.N,/Power_Control/PWR_BTN_TRIGGER*% X150250000Y-130640000D03* %TD*% -D16* +D17* %TO.P,R_GATE1,1*% %TO.N,VSYS*% X148520000Y-114500000D03* @@ -426,7 +434,7 @@ X148520000Y-114500000D03* %TO.N,/Power_Control/PWR_GATE*% X147500000Y-114500000D03* %TD*% -D18* +D19* %TO.P,Q_LATCH1,1,G_1*% %TO.N,/Power_Control/PWR_LATCH_G*% X148500000Y-121900000D03* @@ -437,7 +445,7 @@ X148500000Y-120000000D03* %TO.N,/Power_Control/PWR_GATE*% X150375000Y-120950000D03* %TD*% -D22* +D10* %TO.P,C_SYS_2,1*% %TO.N,VSYS*% X135500000Y-117000000D03* @@ -450,7 +458,7 @@ D30* %TO.N,*% X150400000Y-105200000D03* %TD*% -D17* +D18* %TO.P,C_BAT1,1*% %TO.N,VBAT*% X136500000Y-120500000D03* @@ -548,7 +556,7 @@ X122525000Y-114740000D03* %TO.N,GND*% X122525000Y-115760000D03* %TD*% -D16* +D17* %TO.P,R_VSET1,1*% %TO.N,/Power_Charger/CHG_VSET*% X126020000Y-122500000D03* @@ -631,7 +639,7 @@ X137650000Y-77810000D03* %TO.N,GND*% X137650000Y-76850000D03* %TD*% -D18* +D19* %TO.P,Q_INV1,1,B_1*% %TO.N,/Power_Control/PWR_BTN_INV_BASE*% X145850000Y-126850000D03* @@ -642,7 +650,7 @@ X145850000Y-124950000D03* %TO.N,/Power_Control/PWR_BTN_TRIGGER*% X147725000Y-125900000D03* %TD*% -D16* +D17* %TO.P,R_TS1,1*% %TO.N,/Power_Charger/CHG_TS*% X126020000Y-124000000D03* @@ -652,12 +660,12 @@ X125000000Y-124000000D03* %TD*% D41* %TO.N,3V3*% -X149550000Y-132950000D03* X139342332Y-122557668D03* X122500000Y-107500000D03* X127110000Y-120400000D03* X151500000Y-153000000D03* X135500000Y-88000000D03* +X149550000Y-132950000D03* X148000000Y-91500000D03* X142550000Y-79650000D03* X138600000Y-146500000D03* @@ -812,30 +820,26 @@ X133588870Y-113975000D03* X143000000Y-114500000D03* X133850000Y-111000000D03* %TD*% -%TO.N,/MCU_Core/PWR_BTN_SENSE*% +%TO.N,/Power_Control/PWR_LATCH_G*% D42* -X154100000Y-81100000D02* -X154400000Y-81400000D01* -X154400000Y-81400000D02* -X154400000Y-129200000D01* -X154400000Y-129200000D02* -X150600000Y-133000000D01* -X150600000Y-133000000D02* -X150600000Y-133800000D01* -X150600000Y-133800000D02* -X149950000Y-134450000D01* -X149950000Y-134450000D02* -X148540000Y-134450000D01* -X148540000Y-134450000D02* -X148140000Y-134850000D01* +X146450000Y-120760000D02* +X146450000Y-121350000D01* +X146450000Y-121350000D02* +X146150000Y-121650000D01* +%TO.N,GND*% +X146450000Y-119800000D02* +X146700000Y-119800000D01* +X146700000Y-119800000D02* +X147500000Y-119000000D01* %TO.N,3V3*% +D43* +X127510000Y-120000000D02* +X127110000Y-120400000D01* +D42* X149170000Y-133330000D02* X149550000Y-132950000D01* X149170000Y-133700000D02* X149170000Y-133330000D01* -D43* -X127510000Y-120000000D02* -X127110000Y-120400000D01* D44* X122025000Y-109050000D02* X122025000Y-107975000D01* @@ -1390,24 +1394,38 @@ D42* X151500000Y-85000000D02* X151500000Y-78000000D01* %TO.N,/MCU_Core/PWR_BTN_SENSE*% +X154400000Y-129200000D02* +X150600000Y-133000000D01* X145980000Y-137500000D02* X136480000Y-147000000D01* +X150600000Y-133000000D02* +X150600000Y-133800000D01* X147840000Y-135640000D02* X147840000Y-135150000D01* +X148540000Y-134450000D02* +X148140000Y-134850000D01* X147840000Y-135640000D02* X145980000Y-137500000D01* X147100000Y-133700000D02* X146100000Y-132700000D01* X122984500Y-152484500D02* X125000000Y-154500000D01* +X150600000Y-133800000D02* +X149950000Y-134450000D01* X148140000Y-134850000D02* X148140000Y-133710000D01* X147840000Y-135150000D02* X148140000Y-134850000D01* +X154100000Y-81100000D02* +X154400000Y-81400000D01* +X149950000Y-134450000D02* +X148540000Y-134450000D01* X148150000Y-133700000D02* X147100000Y-133700000D01* X125063866Y-147000000D02* X122984500Y-149079366D01* +X154400000Y-81400000D02* +X154400000Y-129200000D01* X148140000Y-133710000D02* X148150000Y-133700000D01* X122984500Y-149079366D02* diff --git a/PCB/production/gerbers/snips_controller-B_Mask.gbr b/PCB/production/gerbers/snips_controller-B_Mask.gbr index 2fb8d06..6b8782c 100644 --- a/PCB/production/gerbers/snips_controller-B_Mask.gbr +++ b/PCB/production/gerbers/snips_controller-B_Mask.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:54-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Soldermask,Bot*% %TF.FilePolarity,Negative*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* @@ -30,22 +30,22 @@ G04 Aperture macros list* 20,1,$1+$1,$8,$9,$2,$3,0*% G04 Aperture macros list end* %ADD10C,0.010000*% -%ADD11C,1.431000*% -%ADD12C,2.000000*% -%ADD13C,0.900000*% -%ADD14C,0.650000*% -%ADD15O,1.000000X2.100000*% -%ADD16O,1.000000X1.600000*% -%ADD17C,2.750000*% -%ADD18C,2.250000*% -%ADD19C,2.450000*% -%ADD20RoundRect,0.135000X0.135000X0.185000X-0.135000X0.185000X-0.135000X-0.185000X0.135000X-0.185000X0*% -%ADD21RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% -%ADD22RoundRect,0.150000X-0.587500X-0.150000X0.587500X-0.150000X0.587500X0.150000X-0.587500X0.150000X0*% -%ADD23RoundRect,0.112500X-0.112500X0.187500X-0.112500X-0.187500X0.112500X-0.187500X0.112500X0.187500X0*% -%ADD24RoundRect,0.250000X0.350000X0.625000X-0.350000X0.625000X-0.350000X-0.625000X0.350000X-0.625000X0*% -%ADD25O,1.200000X1.750000*% -%ADD26RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*% +%ADD11RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*% +%ADD12C,1.431000*% +%ADD13C,2.000000*% +%ADD14C,0.900000*% +%ADD15C,0.650000*% +%ADD16O,1.000000X2.100000*% +%ADD17O,1.000000X1.600000*% +%ADD18C,2.750000*% +%ADD19C,2.250000*% +%ADD20C,2.450000*% +%ADD21RoundRect,0.135000X0.135000X0.185000X-0.135000X0.185000X-0.135000X-0.185000X0.135000X-0.185000X0*% +%ADD22RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% +%ADD23RoundRect,0.150000X-0.587500X-0.150000X0.587500X-0.150000X0.587500X0.150000X-0.587500X0.150000X0*% +%ADD24RoundRect,0.112500X-0.112500X0.187500X-0.112500X-0.187500X0.112500X-0.187500X0.112500X0.187500X0*% +%ADD25RoundRect,0.250000X0.350000X0.625000X-0.350000X0.625000X-0.350000X-0.625000X0.350000X-0.625000X0*% +%ADD26O,1.200000X1.750000*% %ADD27RoundRect,0.250000X0.250000X0.475000X-0.250000X0.475000X-0.250000X-0.475000X0.250000X-0.475000X0*% %ADD28RoundRect,0.250000X-0.475000X0.250000X-0.475000X-0.250000X0.475000X-0.250000X0.475000X0.250000X0*% %ADD29R,0.300000X0.300000*% @@ -2848,6 +2848,11 @@ X134308000Y-119651000D01* G37* %TD*% D11* +%TO.C,C_LATCH_G1*% +X146450000Y-119800000D03* +X146450000Y-120760000D03* +%TD*% +D12* %TO.C,U_XBEE1*% X142000000Y-127500000D03* X140000000Y-127500000D03* @@ -2870,11 +2875,11 @@ X138000000Y-149500000D03* X140000000Y-149500000D03* X142000000Y-149500000D03* %TD*% -D12* +D13* %TO.C,MHole*% X126500000Y-86000000D03* %TD*% -D13* +D14* %TO.C,SW_TRIG_DIG1*% X126850000Y-61750000D03* X122600000Y-61750000D03* @@ -2883,51 +2888,51 @@ X122600000Y-61750000D03* X121750000Y-88375000D03* X121750000Y-92625000D03* %TD*% -D12* +D13* %TO.C,MHole*% X148500000Y-86000000D03* %TD*% %TO.C,MHole*% X122500000Y-156500000D03* %TD*% -D13* +D14* %TO.C,SW_VOL_DN1*% X153200000Y-102650000D03* X153200000Y-98400000D03* %TD*% -D14* +D15* %TO.C,J_USB1*% X134610000Y-154500000D03* X140390000Y-154500000D03* -D15* -X133180000Y-153970000D03* D16* +X133180000Y-153970000D03* +D17* X133180000Y-158150000D03* -D15* -X141820000Y-153970000D03* D16* +X141820000Y-153970000D03* +D17* X141820000Y-158150000D03* %TD*% -D17* +D18* %TO.C,J_STICK1*% X131175000Y-90250000D03* X131175000Y-100250000D03* X143825000Y-90250000D03* X143825000Y-100250000D03* -D18* +D19* X140000000Y-86520000D03* X146230000Y-97750000D03* X137500000Y-86520000D03* X146230000Y-95250000D03* X135000000Y-86520000D03* X146230000Y-92750000D03* -D19* +D20* X134250000Y-101000000D03* X140750000Y-101000000D03* X134250000Y-105500000D03* X140750000Y-105500000D03* %TD*% -D13* +D14* %TO.C,SW_THR_DN1*% X121750000Y-98400000D03* X121750000Y-102650000D03* @@ -2936,43 +2941,43 @@ X121750000Y-102650000D03* X153200000Y-92625000D03* X153200000Y-88375000D03* %TD*% -D12* +D13* %TO.C,MHole*% X152500000Y-156500000D03* %TD*% -D13* +D14* %TO.C,SW_PWR1*% X126875000Y-157950000D03* X131125000Y-157950000D03* %TD*% -D20* +D21* %TO.C,R_BTN_PU1*% X149170000Y-133700000D03* X148150000Y-133700000D03* %TD*% -D21* +D22* %TO.C,C_SYS_1*% X138000000Y-117000000D03* X139900000Y-117000000D03* %TD*% -D22* +D23* %TO.C,Q_PWR1*% X148625000Y-117950000D03* X148625000Y-116050000D03* X150500000Y-117000000D03* %TD*% -D23* +D24* %TO.C,D_VBUS_TVS1*% X137400000Y-155150000D03* X137400000Y-157250000D03* %TD*% -D24* +D25* %TO.C,BT1*% X152500000Y-68900000D03* -D25* +D26* X150500000Y-68900000D03* %TD*% -D26* +D11* %TO.C,C_VIN_2*% X130000000Y-118040000D03* X130000000Y-119000000D03* @@ -3036,27 +3041,27 @@ X147950000Y-129450000D03* X150250000Y-131660000D03* X150250000Y-130640000D03* %TD*% -D20* +D21* %TO.C,R_GATE1*% X148520000Y-114500000D03* X147500000Y-114500000D03* %TD*% -D22* +D23* %TO.C,Q_LATCH1*% X148500000Y-121900000D03* X148500000Y-120000000D03* X150375000Y-120950000D03* %TD*% -D26* +D11* %TO.C,C_SYS_2*% X135500000Y-117000000D03* X135500000Y-117960000D03* %TD*% -D12* +D13* %TO.C,REF\u002A\u002A*% X150400000Y-105200000D03* %TD*% -D21* +D22* %TO.C,C_BAT1*% X136500000Y-120500000D03* X138400000Y-120500000D03* @@ -3066,7 +3071,7 @@ D34* X137090000Y-122800000D03* X138110000Y-122800000D03* %TD*% -D12* +D13* %TO.C,REF\u002A\u002A*% X125900000Y-95300000D03* %TD*% @@ -3092,7 +3097,7 @@ D37* X122525000Y-114740000D03* X122525000Y-115760000D03* %TD*% -D20* +D21* %TO.C,R_VSET1*% X126020000Y-122500000D03* X125000000Y-122500000D03* @@ -3105,7 +3110,7 @@ X127900000Y-120000000D03* X126040000Y-121000000D03* X125020000Y-121000000D03* %TD*% -D12* +D13* %TO.C,REF\u002A\u002A*% X122800000Y-75700000D03* %TD*% @@ -3141,13 +3146,13 @@ D38* X137650000Y-77810000D03* X137650000Y-76850000D03* %TD*% -D22* +D23* %TO.C,Q_INV1*% X145850000Y-126850000D03* X145850000Y-124950000D03* X147725000Y-125900000D03* %TD*% -D20* +D21* %TO.C,R_TS1*% X126020000Y-124000000D03* X125000000Y-124000000D03* diff --git a/PCB/production/gerbers/snips_controller-B_Paste.gbr b/PCB/production/gerbers/snips_controller-B_Paste.gbr index a8bc48f..070d3d6 100644 --- a/PCB/production/gerbers/snips_controller-B_Paste.gbr +++ b/PCB/production/gerbers/snips_controller-B_Paste.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:54-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Paste,Bot*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* @@ -30,11 +30,11 @@ G04 Aperture macros list* 20,1,$1+$1,$8,$9,$2,$3,0*% G04 Aperture macros list end* %ADD10C,0.010000*% -%ADD11RoundRect,0.135000X0.135000X0.185000X-0.135000X0.185000X-0.135000X-0.185000X0.135000X-0.185000X0*% -%ADD12RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% -%ADD13RoundRect,0.150000X-0.587500X-0.150000X0.587500X-0.150000X0.587500X0.150000X-0.587500X0.150000X0*% -%ADD14RoundRect,0.112500X-0.112500X0.187500X-0.112500X-0.187500X0.112500X-0.187500X0.112500X0.187500X0*% -%ADD15RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*% +%ADD11RoundRect,0.140000X-0.170000X0.140000X-0.170000X-0.140000X0.170000X-0.140000X0.170000X0.140000X0*% +%ADD12RoundRect,0.135000X0.135000X0.185000X-0.135000X0.185000X-0.135000X-0.185000X0.135000X-0.185000X0*% +%ADD13RoundRect,0.250000X-0.250000X-0.475000X0.250000X-0.475000X0.250000X0.475000X-0.250000X0.475000X0*% +%ADD14RoundRect,0.150000X-0.587500X-0.150000X0.587500X-0.150000X0.587500X0.150000X-0.587500X0.150000X0*% +%ADD15RoundRect,0.112500X-0.112500X0.187500X-0.112500X-0.187500X0.112500X-0.187500X0.112500X0.187500X0*% %ADD16RoundRect,0.250000X0.250000X0.475000X-0.250000X0.475000X-0.250000X-0.475000X0.250000X-0.475000X0*% %ADD17RoundRect,0.250000X-0.475000X0.250000X-0.475000X-0.250000X0.475000X-0.250000X0.475000X0.250000X0*% %ADD18R,0.300000X0.300000*% @@ -306,27 +306,32 @@ X133383000Y-118311000D01* G37* %TD*% D11* +%TO.C,C_LATCH_G1*% +X146450000Y-119800000D03* +X146450000Y-120760000D03* +%TD*% +D12* %TO.C,R_BTN_PU1*% X149170000Y-133700000D03* X148150000Y-133700000D03* %TD*% -D12* +D13* %TO.C,C_SYS_1*% X138000000Y-117000000D03* X139900000Y-117000000D03* %TD*% -D13* +D14* %TO.C,Q_PWR1*% X148625000Y-117950000D03* X148625000Y-116050000D03* X150500000Y-117000000D03* %TD*% -D14* +D15* %TO.C,D_VBUS_TVS1*% X137400000Y-155150000D03* X137400000Y-157250000D03* %TD*% -D15* +D11* %TO.C,C_VIN_2*% X130000000Y-118040000D03* X130000000Y-119000000D03* @@ -390,23 +395,23 @@ X147950000Y-129450000D03* X150250000Y-131660000D03* X150250000Y-130640000D03* %TD*% -D11* +D12* %TO.C,R_GATE1*% X148520000Y-114500000D03* X147500000Y-114500000D03* %TD*% -D13* +D14* %TO.C,Q_LATCH1*% X148500000Y-121900000D03* X148500000Y-120000000D03* X150375000Y-120950000D03* %TD*% -D15* +D11* %TO.C,C_SYS_2*% X135500000Y-117000000D03* X135500000Y-117960000D03* %TD*% -D12* +D13* %TO.C,C_BAT1*% X136500000Y-120500000D03* X138400000Y-120500000D03* @@ -444,7 +449,7 @@ D25* X122525000Y-114740000D03* X122525000Y-115760000D03* %TD*% -D11* +D12* %TO.C,R_VSET1*% X126020000Y-122500000D03* X125000000Y-122500000D03* @@ -489,13 +494,13 @@ D26* X137650000Y-77810000D03* X137650000Y-76850000D03* %TD*% -D13* +D14* %TO.C,Q_INV1*% X145850000Y-126850000D03* X145850000Y-124950000D03* X147725000Y-125900000D03* %TD*% -D11* +D12* %TO.C,R_TS1*% X126020000Y-124000000D03* X125000000Y-124000000D03* diff --git a/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr b/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr index 53e9ffd..0a1299f 100644 --- a/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr +++ b/PCB/production/gerbers/snips_controller-B_Silkscreen.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:54-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Legend,Bot*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* @@ -1617,8 +1617,13 @@ X153256077Y-76319819D02* X152922744Y-77319819D01* X152922744Y-77319819D02* X152589411Y-76319819D01* -%TO.C,R_BTN_PU1*% +%TO.C,C_LATCH_G1*% D12* +X146090000Y-120172164D02* +X146090000Y-120387836D01* +X146810000Y-120172164D02* +X146810000Y-120387836D01* +%TO.C,R_BTN_PU1*% X148813641Y-133320000D02* X148506359Y-133320000D01* X148813641Y-134080000D02* diff --git a/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr b/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr index a165cda..bb0d375 100644 --- a/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr +++ b/PCB/production/gerbers/snips_controller-Edge_Cuts.gbr @@ -1,11 +1,11 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:54-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Profile,NP*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* diff --git a/PCB/production/gerbers/snips_controller-F_Cu.gbr b/PCB/production/gerbers/snips_controller-F_Cu.gbr index 4dc8a4a..952da1f 100644 --- a/PCB/production/gerbers/snips_controller-F_Cu.gbr +++ b/PCB/production/gerbers/snips_controller-F_Cu.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:53-07:00*% +%TF.CreationDate,2026-09-23T21:51:54-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Copper,L1,Top*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:54* %MOMM*% %LPD*% G01* @@ -898,12 +898,12 @@ X150160000Y-63000000D03* %TD*% D54* %TO.N,3V3*% -X149550000Y-132950000D03* X139342332Y-122557668D03* X122500000Y-107500000D03* X127110000Y-120400000D03* X151500000Y-153000000D03* X135500000Y-88000000D03* +X149550000Y-132950000D03* X148000000Y-91500000D03* X142550000Y-79650000D03* X138600000Y-146500000D03* diff --git a/PCB/production/gerbers/snips_controller-F_Mask.gbr b/PCB/production/gerbers/snips_controller-F_Mask.gbr index 17641c0..5cf88c0 100644 --- a/PCB/production/gerbers/snips_controller-F_Mask.gbr +++ b/PCB/production/gerbers/snips_controller-F_Mask.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:54-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Soldermask,Top*% %TF.FilePolarity,Negative*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* diff --git a/PCB/production/gerbers/snips_controller-F_Paste.gbr b/PCB/production/gerbers/snips_controller-F_Paste.gbr index fd7fe61..7cb7b07 100644 --- a/PCB/production/gerbers/snips_controller-F_Paste.gbr +++ b/PCB/production/gerbers/snips_controller-F_Paste.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:53-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Paste,Top*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* diff --git a/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr b/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr index 48f6c9c..bdda738 100644 --- a/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr +++ b/PCB/production/gerbers/snips_controller-F_Silkscreen.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:54-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Legend,Top*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:54* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* diff --git a/PCB/production/gerbers/snips_controller-In1_Cu.gbr b/PCB/production/gerbers/snips_controller-In1_Cu.gbr index 6e7ea18..c53497a 100644 --- a/PCB/production/gerbers/snips_controller-In1_Cu.gbr +++ b/PCB/production/gerbers/snips_controller-In1_Cu.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:53-07:00*% +%TF.CreationDate,2026-09-23T21:51:54-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Copper,L2,Inr*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:54* %MOMM*% %LPD*% G01* @@ -174,12 +174,12 @@ X150160000Y-63000000D03* %TD*% D21* %TO.N,3V3*% -X149550000Y-132950000D03* X139342332Y-122557668D03* X122500000Y-107500000D03* X127110000Y-120400000D03* X151500000Y-153000000D03* X135500000Y-88000000D03* +X149550000Y-132950000D03* X148000000Y-91500000D03* X142550000Y-79650000D03* X138600000Y-146500000D03* diff --git a/PCB/production/gerbers/snips_controller-In2_Cu.gbr b/PCB/production/gerbers/snips_controller-In2_Cu.gbr index 619a591..966d529 100644 --- a/PCB/production/gerbers/snips_controller-In2_Cu.gbr +++ b/PCB/production/gerbers/snips_controller-In2_Cu.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:17:53-07:00*% +%TF.CreationDate,2026-09-23T21:51:55-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Copper,L3,Inr*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:17:53* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:51:55* %MOMM*% %LPD*% G01* @@ -174,12 +174,12 @@ X150160000Y-63000000D03* %TD*% D21* %TO.N,3V3*% -X149550000Y-132950000D03* X139342332Y-122557668D03* X122500000Y-107500000D03* X127110000Y-120400000D03* X151500000Y-153000000D03* X135500000Y-88000000D03* +X149550000Y-132950000D03* X148000000Y-91500000D03* X142550000Y-79650000D03* X138600000Y-146500000D03* diff --git a/PCB/production/gerbers/snips_controller-NPTH.drl b/PCB/production/gerbers/snips_controller-NPTH.drl index f7586e5..63d2181 100644 --- a/PCB/production/gerbers/snips_controller-NPTH.drl +++ b/PCB/production/gerbers/snips_controller-NPTH.drl @@ -1,7 +1,7 @@ M48 -; DRILL file KiCad 10.0.5 date 2026-09-23T21:17:50 +; DRILL file KiCad 10.0.5 date 2026-09-23T21:51:53 ; FORMAT={-:-/ absolute / metric / decimal} -; #@! TF.CreationDate,2026-09-23T21:17:50-07:00 +; #@! TF.CreationDate,2026-09-23T21:51:53-07:00 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5 ; #@! TF.FileFunction,NonPlated,1,4,NPTH FMAT,2 diff --git a/PCB/production/gerbers/snips_controller-PTH.drl b/PCB/production/gerbers/snips_controller-PTH.drl index f0c99fd..ec78edb 100644 --- a/PCB/production/gerbers/snips_controller-PTH.drl +++ b/PCB/production/gerbers/snips_controller-PTH.drl @@ -1,7 +1,7 @@ M48 -; DRILL file KiCad 10.0.5 date 2026-09-23T21:17:50 +; DRILL file KiCad 10.0.5 date 2026-09-23T21:51:53 ; FORMAT={-:-/ absolute / metric / decimal} -; #@! TF.CreationDate,2026-09-23T21:17:50-07:00 +; #@! TF.CreationDate,2026-09-23T21:51:53-07:00 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5 ; #@! TF.FileFunction,Plated,1,4,PTH FMAT,2 diff --git a/PCB/production/gerbers/snips_controller-job.gbrjob b/PCB/production/gerbers/snips_controller-job.gbrjob index 1bf2ebb..aeb195e 100644 --- a/PCB/production/gerbers/snips_controller-job.gbrjob +++ b/PCB/production/gerbers/snips_controller-job.gbrjob @@ -5,7 +5,7 @@ "Application": "Pcbnew", "Version": "10.0.5" }, - "CreationDate": "2026-09-23T21:17:54-07:00" + "CreationDate": "2026-09-23T21:51:55-07:00" }, "GeneralSpecs": { "ProjectId": { diff --git a/PCB/production/jlcpcb/Snips_1_1.zip b/PCB/production/jlcpcb/Snips_1_1.zip index 9db07d2..9d42b5f 100644 Binary files a/PCB/production/jlcpcb/Snips_1_1.zip and b/PCB/production/jlcpcb/Snips_1_1.zip differ diff --git a/PCB/production/jlcpcb/netlist.ipc b/PCB/production/jlcpcb/netlist.ipc index 05e495e..521cdc8 100644 --- a/PCB/production/jlcpcb/netlist.ipc +++ b/PCB/production/jlcpcb/netlist.ipc @@ -1,12 +1,12 @@ P CODE 00 P UNITS CUST 0 P arrayDim N -3173V3 VIA MD0118PA00X+058878Y-052343X0236Y0000R000S3 3173V3 VIA MD0118PA00X+054859Y-048251X0236Y0000R000S3 3173V3 VIA MD0118PA00X+048228Y-042323X0236Y0000R000S3 3173V3 VIA MD0118PA00X+050043Y-047402X0236Y0000R000S3 3173V3 VIA MD0118PA00X+059646Y-060236X0236Y0000R000S3 3173V3 VIA MD0118PA00X+053346Y-034646X0236Y0000R000S3 +3173V3 VIA MD0118PA00X+058878Y-052343X0236Y0000R000S3 3173V3 VIA MD0118PA00X+058268Y-036024X0236Y0000R000S3 3173V3 VIA MD0118PA00X+056122Y-031358X0236Y0000R000S3 3173V3 VIA MD0118PA00X+054567Y-057677X0236Y0000R000S3 @@ -128,6 +128,8 @@ P arrayDim N 317ER_BUCK/PWR_EN VIA MD0118PA00X+052594Y-044872X0236Y0000R000S3 317ER_BUCK/PWR_EN VIA MD0118PA00X+056299Y-045079X0236Y0000R000S3 317ER_BUCK/PWR_EN VIA MD0118PA00X+052697Y-043701X0236Y0000R000S3 +327GND C_LATC-1 A04X+057657Y-047165X0220Y0244R090S1 +327OL/PWR_LATCH_G C_LATC-2 A04X+057657Y-047543X0220Y0244R090S1 3173V3 U_XBEE-1 D0362PA00X+055906Y-050197X0563Y0000R090S0 317SH}DIO13-PAD2) U_XBEE-2 D0362PA00X+055118Y-050197X0563Y0000R090S0 317SH}DIO14-PAD3) U_XBEE-3 D0362PA00X+054331Y-050197X0563Y0000R090S0 diff --git a/PCB/production/placement/snips_controller-pnp_bottom.gbr b/PCB/production/placement/snips_controller-pnp_bottom.gbr index 32bb045..c1078c0 100644 --- a/PCB/production/placement/snips_controller-pnp_bottom.gbr +++ b/PCB/production/placement/snips_controller-pnp_bottom.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:18:22-07:00*% +%TF.CreationDate,2026-09-23T21:52:27-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Component,L4,Bot*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:18:22* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:52:27* %MOMM*% %LPD*% G01* @@ -25,6 +25,27 @@ G04 APERTURE LIST* %TD*% G04 APERTURE END LIST* D10* +%TO.C,C_LATCH_G1*% +%TO.CFtp,C_0402_1005Metric*% +%TO.CVal,100nF*% +%TO.CLbN,Capacitor_SMD*% +%TO.CMnt,SMD*% +%TO.CRot,90*% +X146450000Y-120280000D03* +D11* +X146905000Y-119375000D02* +X146905000Y-121185000D01* +X145995000Y-121185000D01* +X145995000Y-119375000D01* +X146905000Y-119375000D01* +D12* +%TO.P,C_LATCH_G1,1*% +X146450000Y-119800000D03* +D13* +%TO.P,C_LATCH_G1,2*% +X146450000Y-120760000D03* +%TD*% +D10* %TO.C,R_BTN_PU1*% %TO.CFtp,R_0402_1005Metric*% %TO.CVal,100kΩ*% diff --git a/PCB/production/placement/snips_controller-pnp_top.gbr b/PCB/production/placement/snips_controller-pnp_top.gbr index 9e8ed78..b4c3ff1 100644 --- a/PCB/production/placement/snips_controller-pnp_top.gbr +++ b/PCB/production/placement/snips_controller-pnp_top.gbr @@ -1,12 +1,12 @@ %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*% -%TF.CreationDate,2026-09-23T21:18:22-07:00*% +%TF.CreationDate,2026-09-23T21:52:27-07:00*% %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*% %TF.SameCoordinates,Original*% %TF.FileFunction,Component,L1,Top*% %TF.FilePolarity,Positive*% %FSLAX46Y46*% G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* -G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:18:22* +G04 Created by KiCad (PCBNEW 10.0.5) date 2026-09-23 21:52:27* %MOMM*% %LPD*% G01* diff --git a/PCB/snips_controller.kicad_pcb b/PCB/snips_controller.kicad_pcb index ea9daf7..68c7ea0 100644 --- a/PCB/snips_controller.kicad_pcb +++ b/PCB/snips_controller.kicad_pcb @@ -18974,6 +18974,213 @@ ) ) ) + (footprint "Capacitor_SMD:C_0402_1005Metric" + (layer "B.Cu") + (uuid "4e27a88d-92dc-4ad8-a165-91c4850ee113") + (at 146.45 120.28 -90) + (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)") + (tags "capacitor") + (property "Reference" "C_LATCH_G1" + (at 0 1.16 90) + (layer "B.SilkS") + (hide yes) + (uuid "ecfae137-6912-4214-8af2-cc03e66f6eca") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property "Value" "100nF" + (at 0 -1.16 90) + (layer "B.Fab") + (uuid "c6ee5121-2a7c-4dd9-9b93-9f86adb06fd3") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "B.Fab") + (hide yes) + (uuid "7bc69b08-bdd5-4058-a028-deb2c55168fe") + (effects + (font + (size 1.27 1.27) + ) + (justify mirror) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "B.Fab") + (hide yes) + (uuid "aa80cf9d-f327-4dab-a2e0-26af10133c25") + (effects + (font + (size 1.27 1.27) + ) + (justify mirror) + ) + ) + (property "KiLib_Generator" "SMD_2terminal_chip_molded" + (at 0 0 90) + (layer "B.SilkS") + (hide yes) + (uuid "2f699639-ed1d-438a-afca-89488baf1b41") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property "MF" "Samsung Electro-Mechanics" + (at 0 0 90) + (unlocked yes) + (layer "B.Fab") + (hide yes) + (uuid "a2022849-d32b-4d95-885f-9c5734c3c89c") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property "Manufacturer_Part_Number" "CL05B104KO5NNNC" + (at 0 0 90) + (unlocked yes) + (layer "B.Fab") + (hide yes) + (uuid "0008b39f-9acd-4afa-a81f-54653426542d") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property "LCSC" "C1525" + (at 0 0 90) + (unlocked yes) + (layer "B.Fab") + (hide yes) + (uuid "a51e1656-3e31-4eec-af31-599785984c2a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + (justify mirror) + ) + ) + (property ki_fp_filters "C_*") + (path "/081a4841-1e21-4908-a8a8-37f54f8809f6/526a9667-117d-48b5-85bd-c2e58526ea56") + (sheetname "/Power_Control/") + (sheetfile "power_control.kicad_sch") + (units + (unit + (name "A") + (pins "1" "2") + ) + ) + (attr smd) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -0.107836 0.36) + (end 0.107836 0.36) + (stroke + (width 0.12) + (type solid) + ) + (layer "B.SilkS") + (uuid "21e574b4-5d89-4874-85a6-d1c7c4df71b7") + ) + (fp_line + (start -0.107836 -0.36) + (end 0.107836 -0.36) + (stroke + (width 0.12) + (type solid) + ) + (layer "B.SilkS") + (uuid "e29432ba-e417-4b9c-bf5a-a03af637d8e5") + ) + (fp_rect + (start -0.91 0.46) + (end 0.91 -0.46) + (stroke + (width 0.05) + (type solid) + ) + (fill no) + (layer "B.CrtYd") + (uuid "6a2c0f50-f981-4cec-881b-ebdc2ef25c31") + ) + (fp_rect + (start -0.5 0.25) + (end 0.5 -0.25) + (stroke + (width 0.1) + (type solid) + ) + (fill no) + (layer "B.Fab") + (uuid "17be7a10-2cb5-4944-8207-7dcacc8746ca") + ) + (fp_text user "${REFERENCE}" + (at 0 0 90) + (layer "B.Fab") + (uuid "18f16315-58b8-458c-9035-23f5c37ec170") + (effects + (font + (size 0.25 0.25) + (thickness 0.04) + ) + (justify mirror) + ) + ) + (pad "1" smd roundrect + (at -0.48 0 270) + (size 0.56 0.62) + (layers "B.Cu" "B.Mask" "B.Paste") + (roundrect_rratio 0.25) + (net "GND") + (pintype "passive") + (uuid "252cee43-10ea-4a63-8bb8-1d0759909799") + ) + (pad "2" smd roundrect + (at 0.48 0 270) + (size 0.56 0.62) + (layers "B.Cu" "B.Mask" "B.Paste") + (roundrect_rratio 0.25) + (net "/Power_Control/PWR_LATCH_G") + (pintype "passive") + (uuid "29110f8f-92e9-4aad-b289-224696c804ba") + ) + (embedded_fonts no) + (model "${KICAD10_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) (footprint "Capacitor_SMD:C_0402_1005Metric" (layer "B.Cu") (uuid "5afd9c51-ad9d-481b-b003-54bbbb6854d6") @@ -28724,6 +28931,14 @@ (net "GND") (uuid "96d05ce3-37bd-4935-ab4a-abecd93d748f") ) + (segment + (start 146.7 119.8) + (end 147.5 119) + (width 0.2) + (layer "B.Cu") + (net "GND") + (uuid "974c5cb1-2b08-4a54-97b8-b8542d129e1c") + ) (segment (start 126.1 118) (end 125 118) @@ -28740,6 +28955,14 @@ (net "GND") (uuid "9d7b83c9-13d0-460d-bfc6-cbd52dec2d56") ) + (segment + (start 146.45 119.8) + (end 146.7 119.8) + (width 0.2) + (layer "B.Cu") + (net "GND") + (uuid "a35fad30-7d21-4e74-bc07-2dcfd21a2acd") + ) (segment (start 139 120.5) (end 139.5 120) @@ -35260,6 +35483,14 @@ (net "/Power_Control/PWR_LATCH_G") (uuid "34c416ef-b0d5-4859-aeec-869d533a6ee8") ) + (segment + (start 146.45 121.35) + (end 146.15 121.65) + (width 0.2) + (layer "B.Cu") + (net "/Power_Control/PWR_LATCH_G") + (uuid "553464fd-6bef-4d3c-8c81-2608ca2ea93a") + ) (segment (start 147.45 122.95) (end 148.5 121.9) @@ -35308,6 +35539,14 @@ (net "/Power_Control/PWR_LATCH_G") (uuid "ada7db08-7884-4aae-b5f3-06727711dbae") ) + (segment + (start 146.45 120.76) + (end 146.45 121.35) + (width 0.2) + (layer "B.Cu") + (net "/Power_Control/PWR_LATCH_G") + (uuid "afddaa42-7b06-4527-a313-2f0ab824fc46") + ) (segment (start 148.05 122.95) (end 150.25 125.15) diff --git a/PCB/snips_controller.kicad_pcb.zip b/PCB/snips_controller.kicad_pcb.zip index 215a17d..504a235 100644 Binary files a/PCB/snips_controller.kicad_pcb.zip and b/PCB/snips_controller.kicad_pcb.zip differ diff --git a/PCB/snips_controller.kicad_pro b/PCB/snips_controller.kicad_pro index f50c202..cea0a6e 100644 --- a/PCB/snips_controller.kicad_pro +++ b/PCB/snips_controller.kicad_pro @@ -680,7 +680,7 @@ "uuid": "21935953-32a0-46ad-8079-8177920c6978" } ], - "used_designators": "R_ISET1,U_OLED1,SW_THR_DN1,SW_THR_UP1,R_XBEE_RST1,PF_VBUS1,J_USB1,PF_VBAT1,Q_PWR1,R_RGB1,R_USB_DP1,R_I2C_SCL1,U_BUCK1,SW_TRIG_DIG1,R_TS1,R_GATE1,C_RGB1,SW_PWR1,PF_GND1,R_XBEE_RC1,C_BUCK_IN1,R_PWR_SENSE1,R_I2C_SDA1,R_VSET1,SW_VOL_UP1,R_BTN_PU1,SW_BOOT1,R_EN_PU1,U_ACCEL1,PF_VSYS1,U_CHG1,R_BOOT_PU1,R_USB_DM1,U_XBEE1,C_STICK1,R_LATCH_G1,SW_VOL_DN1,D_RGB1,Q_LATCH1,L_BUCK1,C_HALL1,U_HALL1,C_XBEE_VCC1,C_BUCK_OUT1,C_XBEE_RC1,C_DBNC1,J_STICK1,C_BAT1,U_MCU1", + "used_designators": "R_ISET1,U_OLED1,SW_THR_DN1,SW_THR_UP1,R_XBEE_RST1,PF_VBUS1,J_USB1,PF_VBAT1,Q_PWR1,R_RGB1,R_USB_DP1,R_I2C_SCL1,U_BUCK1,SW_TRIG_DIG1,R_TS1,R_GATE1,C_RGB1,SW_PWR1,PF_GND1,R_XBEE_RC1,C_BUCK_IN1,R_PWR_SENSE1,R_VSET1,R_I2C_SDA1,SW_VOL_UP1,R_BTN_PU1,SW_BOOT1,R_EN_PU1,U_ACCEL1,PF_VSYS1,U_CHG1,R_BOOT_PU1,R_USB_DM1,U_XBEE1,C_STICK1,R_LATCH_G1,SW_VOL_DN1,D_RGB1,U_HALL1,Q_LATCH1,L_BUCK1,C_HALL1,C_DBNC1,C_XBEE_VCC1,C_BUCK_OUT1,C_XBEE_RC1,U_MCU1,C_BAT1,J_STICK1", "variants": [] }, "sheets": [ diff --git a/scripts/spice/README.md b/scripts/spice/README.md new file mode 100644 index 0000000..8490ab0 --- /dev/null +++ b/scripts/spice/README.md @@ -0,0 +1,45 @@ +# SPICE check for the Power_Control soft-latch + +`latch_sim.py` simulates the button, inverter, diode-OR, latch FET and power PMOS from +`PCB/power_control.kicad_sch` and asserts the behavior we need. ERC, DRC and the netlist only prove +the wiring; they cannot show that a gate is driven high enough or that a power-up transient stays +quiet. This was written after exactly that kind of bug got through (see PRs #58-#60). + +```sh +python3 scripts/spice/latch_sim.py # all checks; exit 1 on any failure +python3 scripts/spice/latch_sim.py --cap 0 # without C_LATCH_G1 -> the insertion checks fail +python3 scripts/spice/latch_sim.py --cap 47n # a smaller cap -> fails the gate-margin check +python3 scripts/spice/latch_sim.py --scenario press +``` + +It drives `libngspice`, which KiCad bundles at +`/Applications/KiCad/KiCad.app/Contents/PlugIns/sim/libngspice.dylib` (there is no ngspice CLI). +Set `NGSPICE_LIB` to use a different copy. No Python packages are needed. + +## Checks + +| Scenario | What it asserts | +|---|---| +| `insert` | Battery plugged in with the board off (VSYS 3.0-4.5V, 10us-1ms rise): `PWR_EN` stays under the buck's EN threshold, the latch gate peaks under 0.5V (below the AO3400A's 0.65V minimum threshold), and the board ends off. | +| `press` | A held button turns `PWR_EN` on within 20ms at VSYS 3.0V with worst-case FET thresholds, and at typical/best-case corners. | +| `shutdown` | The 3V3 rail collapsing after shutdown never lifts the latch gate or `PWR_EN`. | + +## Keeping it in sync + +The netlist is written by hand to mirror the schematic. When `power_control.kicad_sch` changes +(values, a new part on the latch/sense/EN nodes, a different FET), update the constants and topology +at the top of `latch_sim.py` and rerun. Treat a red run as a design problem first and a model problem +second, but do sanity-check the model too: an arbitrary 1uF on the EN pin once produced a fake +100ms glitch. + +## What it does not model + +- Generic SPICE models, not vendor ones: a 2N3904-family model for the MMBT3904, a fitted BAT54, + 1N4148, and Level-1 MOSFETs at typical and worst-case gate thresholds. +- VSYS is an ideal source with a clean ramp (no battery impedance, hot-plug bounce, or bulk caps). +- The buck's EN pin is just its pin capacitance; the buck, 3V3 loads and ESP32 boot are not simulated, + so a short `PWR_EN` pulse is judged against the EN threshold only, not against what the MCU would do. +- Temperature, component tolerance and leakage beyond the diode/FET models. + +Bench-confirm on the first real board: scope `PWR_EN` on battery insertion, and confirm a held press +latches at low battery. diff --git a/scripts/spice/latch_sim.py b/scripts/spice/latch_sim.py new file mode 100755 index 0000000..d389e62 --- /dev/null +++ b/scripts/spice/latch_sim.py @@ -0,0 +1,229 @@ +#!/usr/bin/env python3 +"""ngspice check of the Power_Control soft-latch (button -> inverter -> diode-OR -> latch FET -> PMOS). + +Connectivity checks (ERC/DRC/netlist) cannot show that a gate is actually driven high enough or that +a power-up transient stays quiet, so this simulates the circuit and asserts the behavior we need: + + insert battery plugged in with the board off: PWR_EN must not pulse and the latch must stay off + press a held button must turn PWR_EN on quickly, across supply and FET-threshold corners + shutdown the 3V3 rail collapsing after shutdown must not re-trigger the latch + +Uses libngspice, which KiCad bundles (there is no ngspice CLI). Set NGSPICE_LIB to override. + + python3 scripts/spice/latch_sim.py # all scenarios, current design (exit 1 on failure) + python3 scripts/spice/latch_sim.py --cap 0 # without C_LATCH_G1: shows the insertion blip + python3 scripts/spice/latch_sim.py --scenario press -v + +The netlist below mirrors PCB/power_control.kicad_sch by hand. When that sheet changes, update the +values/topology here and rerun. See scripts/spice/README.md for what is and is not modeled. +""" +import argparse +import ctypes +import os +import sys +import tempfile + +LIB_CANDIDATES = [ + os.environ.get("NGSPICE_LIB"), + "/Applications/KiCad/KiCad.app/Contents/PlugIns/sim/libngspice.dylib", + "/opt/homebrew/lib/libngspice.dylib", + "/usr/local/lib/libngspice.dylib", + "libngspice.so", +] + +# Component values, mirroring power_control.kicad_sch (R_BTN_PU1 returns to 3V3, not VSYS). +R_BTN_PU1 = "100k" +C_DBNC1 = "100n" +R_INV_BASE1 = "100k" +R_INV_PU1 = "100k" +R_LATCH_G1 = "1Meg" +R_GATE1 = "100k" +R_PWR_EN_PD1 = "100k" +C_LATCH_G1 = "100n" + +# Pass/fail limits. +MAX_BLIP_MS = 0.1 # PWR_EN above V_EN_HIGH on battery insertion +V_EN_HIGH = 1.2 # TLV62569 EN VIH max +MAX_OFF_LATCHG = 0.5 # latch gate must stay well under the AO3400A's 0.65V minimum threshold when it should be off +MAX_PRESS_MS = 20.0 # button press -> PWR_EN on + +MODELS = """ +.model QMMBT NPN(IS=6.734f XTI=3 EG=1.11 VAF=74.03 BF=416.4 NE=1.259 ISE=6.734f IKF=66.78m XTB=1.5 BR=.7371 NC=2 ISC=0 IKR=0 RC=1 CJC=3.638p MJC=.3085 VJC=.75 FC=.5 CJE=4.493p MJE=.2593 VJE=.75 TR=239.5n TF=301.2p ITF=.4 VTF=4 XTF=2 RB=10) +.model DBAT54 D(IS=1.4e-8 N=1.05 RS=3 CJO=10p M=0.4 VJ=0.5 BV=30) +.model D4148 D(IS=2.52n RS=.568 N=1.752 CJO=4p M=.4 TT=20n) +.model NAO3400 NMOS(LEVEL=1 VTO={VTHN} KP=5 LAMBDA=0.01) +.model PAO3401 PMOS(LEVEL=1 VTO={-VTHP} KP=4 LAMBDA=0.01) +.model SWM SW(RON=1 ROFF=1G VT=0.5 VH=0.1) +""" + +_ng = None +_callbacks = [] + + +def _load(): + global _ng + if _ng is not None: + return _ng + lib = None + for path in LIB_CANDIDATES: + if not path: + continue + try: + lib = ctypes.CDLL(path) + break + except OSError: + continue + if lib is None: + sys.exit("libngspice not found. Install KiCad or set NGSPICE_LIB to a libngspice shared library.") + send = ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_char_p, ctypes.c_int, ctypes.c_void_p) + exit_ = ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int, ctypes.c_bool, ctypes.c_bool, ctypes.c_int, ctypes.c_void_p) + data = ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_void_p, ctypes.c_int, ctypes.c_int, ctypes.c_void_p) + cbs = [ + send(lambda s, i, u: 0), # stdout/stderr text + send(lambda s, i, u: 0), # status text + exit_(lambda a, b, c, i, u: 0), + data(lambda a, b, c, d: 0), + data(lambda a, b, c, d: 0), + ] + _callbacks.extend(cbs) # keep alive + lib.ngSpice_Init(cbs[0], cbs[1], cbs[2], cbs[3], cbs[4], ctypes.c_void_p(0), None) + _ng = lib + return lib + + +def netlist(vthn, vthp, cap, vsys_pwl, v3v3_pwl, sw_pwl, ic, tstop, tstep, r_rail="1k"): + mitigation = f"Clatch latchg 0 {cap}" if cap else "* no C_LATCH_G1" + return f"""* Power_Control soft-latch +.param VTHN={vthn} VTHP={vthp} +{MODELS} +Vsys vsys 0 PWL({vsys_pwl}) +* 3V3 rail: an ideal source behind r_rail (small = hard-driven/grounded, large = weak) +V3 v3src 0 PWL({v3v3_pwl}) +R3 v3src v3v3 {r_rail} +C3 v3v3 0 10u +* button node +Rbtn v3v3 sense {R_BTN_PU1} +Cdb sense 0 {C_DBNC1} +Ssw sense 0 swc 0 SWM +Vsw swc 0 PWL({sw_pwl}) +* inverter: own VSYS pull-up on the base, isolated from the sense node by a Schottky +Ribase vsys base {R_INV_BASE1} +Diso base sense DBAT54 +Q1 trig base 0 QMMBT +Ripu vsys trig {R_INV_PU1} +* diode-OR into the latch gate (D_OR2 = MCU hold, held low here: MCU is off) +Dor1 trig latchg D4148 +Dor2 hold latchg D4148 +Vhold hold 0 0 +Rlg latchg 0 {R_LATCH_G1} +{mitigation} +Mlatch pwrgate latchg 0 0 NAO3400 W=1 L=1 +Cgs1 latchg 0 550p +Cgd1 latchg pwrgate 75p +* power switch and buck EN (pin capacitance only) +Rgate vsys pwrgate {R_GATE1} +Mpwr pwren pwrgate vsys vsys PAO3401 W=1 L=1 +Cgs2 pwrgate vsys 500p +Rpd pwren 0 {R_PWR_EN_PD1} +Cen pwren 0 20p +{ic} +.tran {tstep} {tstop} uic +.end +""" + + +def simulate(**kw): + """Run one transient. Returns (time list, {node: values}).""" + ng = _load() + ng.ngSpice_Command(b"destroy all") + lines = [l.encode() for l in netlist(**kw).strip().split("\n")] + [None] + arr = (ctypes.c_char_p * len(lines))(*lines) + ng.ngSpice_Circ(arr) + ng.ngSpice_Command(b"run") + nodes = ["sense", "base", "trig", "latchg", "pwrgate", "pwren", "v3v3"] + with tempfile.TemporaryDirectory() as d: + out = os.path.join(d, "out.txt") + ng.ngSpice_Command(f"wrdata {out} {' '.join(f'v({n})' for n in nodes)}".encode()) + rows = [[float(x) for x in line.split()] for line in open(out)] + t = [r[0] for r in rows] + return t, {n: [r[2 * i + 1] for r in rows] for i, n in enumerate(nodes)} + + +def time_above(t, v, threshold): + return sum(t[i] - t[i - 1] for i in range(1, len(t)) if v[i] > threshold and v[i - 1] > threshold) + + +def first_above(t, v, threshold, after=0.0): + return next((t[i] for i in range(len(t)) if t[i] >= after and v[i] > threshold), None) + + +def scenario_insert(cap, verbose): + results = [] + for vsys, rise in ((3.0, "1m"), (3.7, "1m"), (4.2, "100u"), (4.5, "10u")): + t, d = simulate(vthn=1.05, vthp=0.9, cap=cap, tstop="300m", tstep="5u", ic="", + vsys_pwl=f"0 0 {rise} {vsys} 1 {vsys}", v3v3_pwl="0 0", sw_pwl="0 0 1 0") + blip = time_above(t, d["pwren"], V_EN_HIGH) * 1e3 + off = d["latchg"][-1] + peak = max(d["latchg"]) + ok = blip <= MAX_BLIP_MS and off < MAX_OFF_LATCHG and peak < MAX_OFF_LATCHG + results.append((f"insert VSYS={vsys}V", ok, + f"PWR_EN>{V_EN_HIGH}V for {blip:.2f} ms (max {MAX_BLIP_MS}), " + f"peak gate {peak:.2f}V (max {MAX_OFF_LATCHG}), ends off={off < MAX_OFF_LATCHG}")) + return results + + +def scenario_press(cap, verbose): + results = [] + # (VSYS, N-FET Vth, P-FET Vth): worst case at the bottom of the battery, typical, best case + for vsys, vthn, vthp in ((3.0, 1.45, 1.3), (3.7, 1.05, 0.9), (4.2, 0.65, 0.6)): + t, d = simulate(vthn=vthn, vthp=vthp, cap=cap, tstop="600m", tstep="20u", ic="", + vsys_pwl=f"0 0 1m {vsys} 1 {vsys}", v3v3_pwl="0 0", + sw_pwl="0 0 0.1 0 0.1001 1 0.6 1") + on = first_above(t, d["pwren"], V_EN_HIGH, after=0.1) + latency = None if on is None else (on - 0.1) * 1e3 + ok = latency is not None and latency <= MAX_PRESS_MS and d["pwren"][-1] > vsys - 0.3 + results.append((f"press VSYS={vsys}V VthN={vthn}V", + ok, "PWR_EN never came on" if latency is None else + f"PWR_EN on {latency:.1f} ms after press (max {MAX_PRESS_MS}), final {d['pwren'][-1]:.2f}V")) + return results + + +def scenario_shutdown(cap, verbose): + results = [] + for vsys in (3.7, 4.2): + ic = (f".ic v(v3v3)=3.3 v(sense)=3.3 v(vsys)={vsys} v(pwrgate)={vsys} " + "v(base)=0.72 v(trig)=0 v(latchg)=0 v(pwren)=0") + t, d = simulate(vthn=1.05, vthp=0.9, cap=cap, tstop="400m", tstep="20u", ic=ic, + vsys_pwl=f"0 {vsys} 1 {vsys}", v3v3_pwl="0 3.3 10m 3.3 110m 0", sw_pwl="0 0 1 0") + peak = max(d["latchg"]) + ok = peak < MAX_OFF_LATCHG and max(d["pwren"]) < MAX_OFF_LATCHG + results.append((f"shutdown VSYS={vsys}V", ok, + f"peak gate {peak:.2f}V, peak PWR_EN {max(d['pwren']):.2f}V, " + f"lowest button node {min(d['sense']):.2f}V")) + return results + + +SCENARIOS = {"insert": scenario_insert, "press": scenario_press, "shutdown": scenario_shutdown} + + +def main(): + p = argparse.ArgumentParser(description=__doc__, formatter_class=argparse.RawDescriptionHelpFormatter) + p.add_argument("--scenario", choices=[*SCENARIOS, "all"], default="all") + p.add_argument("--cap", default=C_LATCH_G1, + help="C_LATCH_G1 value (SPICE notation, e.g. 47n); 0 removes it. Default: %(default)s") + p.add_argument("-v", "--verbose", action="store_true") + args = p.parse_args() + cap = None if args.cap in ("0", "none", "") else args.cap + + names = SCENARIOS if args.scenario == "all" else [args.scenario] + failed = 0 + for name in names: + for label, ok, detail in SCENARIOS[name](cap, args.verbose): + print(f"{'PASS' if ok else 'FAIL'} {label:32s} {detail}") + failed += not ok + print(f"\n{failed} check(s) failed" if failed else "\nall checks passed") + return 1 if failed else 0 + + +if __name__ == "__main__": + sys.exit(main())