tools: generate the per-CPU SIMD inventory from LLVM's TableGen source

[AdaWorldAPI]

What this adds

tools/gen_llvm_inventory.py builds the per-CPU SIMD feature inventory from LLVM's public TableGen source instead of maintaining it by hand.

• Input: llvm-project's X86.td, AArch64Processors.td and AArch64Features.td, plus the instruction and predicate .td files. They're read at the llvmorg-* tag that matches rustc -vV, which is llvmorg-22.1.8 under the pinned 1.98.1, so the inventory is the one cfg(target_feature) actually sees.
• Resolution: it resolves every processor's feature set: !listconcat / !listremove chains, foreach P = [...] alias blocks, ProcessorAlias, implied-feature closure, aarch64 architecture default extensions, and tune records that imply ISA features.
• Output:
  • tools/llvm-inventory/inventory.json: full per-CPU feature sets for 92 x86 and 99 aarch64 CPUs;
  • .claude/knowledge/llvm-cpu-inventory.md: the readable table. It includes the backend that the simd.rs cfg ladder selects, and which instruction implements each crypto-relevant primitive on that CPU: mul_lo32, variable u32 shift and permute, IFMA, carry-less multiply, and the AES round.
• Primitive rows: they name the LLVM instruction def and its gating predicate, and the generator asserts both still exist in the .td files. An LLVM rename fails the run instead of leaving a stale row.

It follows the gen_ternlog_bodies.py pattern: the output is committed and the script is its provenance.

python3 tools/gen_llvm_inventory.py --write          # regenerate
python3 tools/gen_llvm_inventory.py                  # exit 1 if the committed output is stale
python3 tools/gen_llvm_inventory.py --verify-rustc   # compare every CPU with rustc

Verification

--verify-rustc compares every CPU with rustc's own --print cfg -C target-cpu=.... It covers all features stable rustc exposes: 56 on x86 and 37 on aarch64. It uses rustc's own Rust↔LLVM feature-name table, parsed from rustc_codegen_llvm/src/llvm_util.rs at the pinned release. 191/191 CPUs agree.

The comparator failed first, and each failure drove a real fix:

• evaluating !listremove;
• reading Architecture64's implied list from the right argument;
• including aarch64 architecture default extensions (apple-m4 ssbs);
• the x86_64 ABI baseline (sse/sse2);
• tune records implying ISA features (TuneOryon implies FullFP16, FP16FML and SPE).

I also checked that the staleness mode fails: editing one row makes it exit 1, and regenerating clears it.

What the table shows

• x86-64-v3, the portable baseline, has no aes and no pclmul. Compile-time dispatch on the v3 build cannot reach AES-NI or PCLMULQDQ.
• haswell has pclmul but not aes in LLVM's table.
• arrowlake has avxifma, the VEX-encoded IFMA, without AVX-512.
• aarch64 neoverse-v2 (Graviton4, Grace) and cortex-x925 have no aes, so no hardware AES and no 64-bit PMULL without an explicit +aes.

Not in this PR

• The backend column mirrors the simd.rs cfg ladder by hand; it isn't parsed from simd.rs.
• No wasm rows: wasm has no processor table.
• No CI job runs the staleness check yet.
• LLVM fork: rustc builds on rust-lang's fork of LLVM (rustc/22.1-2026-05-19). Its AArch64 .td files matched the upstream tag byte for byte; --verify-rustc is the guard if that changes.
• No src/ changes. This is the generator's first stage; the missing primitives themselves come in later PRs.

🤖 Generated with Claude Code

https://claude.ai/code/session_019HnekoM1EidTwQLS3oFVFm

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📥 Commits

Reviewing files that changed from the base of the PR and between 07c7b4b and 11de642.

📒 Files selected for processing (4)

• .claude/blackboard.md
• .claude/knowledge/llvm-cpu-inventory.md
• tools/gen_llvm_inventory.py
• tools/llvm-inventory/inventory.json

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