Naming refactor, unified parameter init

edg/abstract_parts/Connectors.py

@@ -32,9 +32,9 @@ def __init__(self) -> None:
 class RfConnectorTestPoint(BlockInterfaceMixin[RfConnector]):
     """Test point mixin that allows the footprint to take a name"""
 
-    def __init__(self, name: StringLike):
+    def __init__(self, tp_name: StringLike):
         super().__init__()
-        self.tp_name = self.ArgParameter(name)
+        self.tp_name = self.ArgParameter(tp_name)
 
 
 class RfConnectorAntenna(Antenna):

edg/abstract_parts/IoController.py

@@ -172,7 +172,7 @@ def connect_port_transformed(self_io: BasePort, inner_io: Callable[[], BasePort]
                 if transform_fn is None:
                     self.connect(self_io, inner_io)
                 else:
-                    connect_port_transformed(self_io, lambda: inner_io, self_io._name_from(self))
+                    connect_port_transformed(self_io, lambda: inner_io, self._path_name_of(self_io))
             else:
                 raise NotImplementedError(f"unknown port type {self_io}")
 
@@ -293,9 +293,7 @@ def _make_pinning(self) -> Mapping[Union[Iterable[str], str], Union[Passive, Has
                 allocation_list.append((io_port.elt_type(), self.get(io_port.requested())))
             elif isinstance(io_port, Port):  # derive Port connections from is_connected
                 if self.get(io_port.is_connected()):
-                    requested = [
-                        self._name_of_child(io_port, self)
-                    ]  # generate requested name from port name if connected
+                    requested = [self._name_of(io_port)]  # generate requested name from port name if connected
                 else:
                     requested = []
                 allocation_list.append((type(io_port), requested))

edg/abstract_parts/IoControllerWrapper.py

@@ -80,8 +80,8 @@ def recurse_port(port: Port, prefix: str) -> None:
             assert prefix not in pin_dict, f"duplicate pin name {prefix}"
             pin_dict[prefix] = port
 
-            for subport_name, subport in port._ports.items():
-                recurse_port(subport, f"{prefix}.{subport_name}")
+            for subport in port._ports:
+                recurse_port(subport, f"{prefix}.{port._name_of(subport)}")
 
         for io_port in self._io_ports:
             if isinstance(io_port, Vector):
@@ -91,7 +91,7 @@ def recurse_port(port: Port, prefix: str) -> None:
                     recurse_port(subport, subport_name)
             elif isinstance(io_port, Port):
                 if self.get(io_port.is_connected()):
-                    port_name = io_port._name_from(self)
+                    port_name = self._path_name_of(io_port)
                     recurse_port(io_port, port_name)
             else:
                 raise NotImplementedError(f"unknown port type {io_port}")
@@ -203,16 +203,16 @@ def recurse_port(port: Port, prefix: str) -> None:
             assert prefix not in pin_type_dict, f"duplicate pin name {prefix}"
             pin_type_dict[prefix] = type(port)
 
-            for subport_name, subport in port._ports.items():
-                recurse_port(subport, f"{prefix}.{subport_name}")
+            for subport in port._ports:
+                recurse_port(subport, f"{prefix}.{port._name_of(subport)}")
 
         for io_port in self._io_ports:
             if isinstance(io_port, Vector):
                 for subport_name in self.get(io_port.requested()):
                     recurse_port(io_port._tpe.empty(), subport_name)
             elif isinstance(io_port, Port):
                 if self.get(io_port.is_connected()):
-                    port_name = io_port._name_from(self)
+                    port_name = self._name_of(io_port)
                     recurse_port(io_port, port_name)
             else:
                 raise NotImplementedError(f"unknown port type {io_port}")

edg/abstract_parts/PinMappable.py

@@ -435,7 +435,8 @@ def try_allocate_resource(
                 resource_model = resource.port_model  # typer gets confused if this is put directly where it is used
                 inner_models = {}
                 resource_name = resource.name  # typer gets confused if this is put directly where it is used
-                for inner_name, inner_model in resource.port_model._ports.items():
+                for inner_model in resource.port_model._ports:
+                    inner_name = resource.port_model._name_of(inner_model)
                     inner_type = type(inner_model)
                     if inner_type in self.transforms:  # apply transform to search for the resource type, if needed
                         inner_type = self.transforms[inner_type][0]

edg/core/Array.py

@@ -155,36 +155,20 @@ def items(self) -> ItemsView[str, VectorType]:
 
     # unlike most other LibraryElement types, the names are stored in _elts and _allocates
     @override
-    def _name_of_child(self, subelt: Any, context: Any, allow_unknown: bool = False) -> str:
-        from .HierarchyBlock import Block
-
-        block_parent = self._block_parent()
-        assert isinstance(block_parent, Block)
-
-        if context is block_parent:
-            # in block defining this port (direct elt definition), or in test top
-            assert self._elts is not None, "can't get name on undefined vector"
+    def _name_of(self, subelt: Any, *, debug: bool = False) -> str:
+        if self._elts is not None:
             for name, elt in self._elts.items():
                 if subelt is elt:
                     return name
-            if allow_unknown:
-                return f"(unknown {subelt.__class__.__name__})"
-            else:
-                raise ValueError(f"no name for {subelt}")
-        elif context is block_parent._parent:
-            # in block enclosing the block defining this port (allocate required)
-            for i, (suggested_name, allocate_elt) in enumerate(self._requests):
-                if subelt is allocate_elt:
-                    if suggested_name is not None:
-                        return suggested_name
-                    else:
-                        return f"_allocate_{i}"
-            if allow_unknown:
-                return f"(unknown {subelt.__class__.__name__})"
-            else:
-                raise ValueError(f"allocated elt not found {subelt}")
-        else:
-            raise ValueError(f"unknown context of array")
+
+        for i, (suggested_name, allocate_elt) in enumerate(self._requests):
+            if subelt is allocate_elt:
+                if suggested_name is not None:
+                    return suggested_name
+                else:
+                    return f"_allocate_{i}"
+
+        raise ValueError(f"{subelt} not in Vector")
 
     @override
     def _get_elt_sample(self) -> BasePort:
@@ -338,14 +322,19 @@ def validate_selector(expected: Type[SelectorType], result: ConstraintExpr) -> S
     # See the note in ArrayExpr for why this is expanded.
     @overload
     def map_extract(self, selector: Callable[[VectorType], BoolExpr]) -> ArrayBoolExpr: ...
+
     @overload
     def map_extract(self, selector: Callable[[VectorType], IntExpr]) -> ArrayIntExpr: ...
+
     @overload
     def map_extract(self, selector: Callable[[VectorType], FloatExpr]) -> ArrayFloatExpr: ...
+
     @overload
     def map_extract(self, selector: Callable[[VectorType], RangeExpr]) -> ArrayRangeExpr: ...
+
     @overload
     def map_extract(self, selector: Callable[[VectorType], StringExpr]) -> ArrayStringExpr: ...
+
     @overload
     def map_extract(self, selector: Callable[[VectorType], ExtractPortType]) -> DerivedVector[ExtractPortType]: ...
 
@@ -377,8 +366,10 @@ def count(self, selector: Callable[[VectorType], BoolExpr]) -> IntExpr:
 
     @overload
     def sum(self, selector: Callable[[VectorType], RangeExpr]) -> RangeExpr: ...
+
     @overload
     def sum(self, selector: Callable[[VectorType], FloatExpr]) -> FloatExpr: ...
+
     def sum(self, selector: Callable[[VectorType], Union[RangeExpr, FloatExpr]]) -> Union[RangeExpr, FloatExpr]:
         param = selector(self._elt_sample)
         if isinstance(param, FloatExpr):

edg/core/BlockInterfaceMixin.py

@@ -1,7 +1,7 @@
 from typing import Generic, Type, List, Optional, get_args, get_origin, Tuple, Callable, Any
 from typing_extensions import TypeVar, override
 
-from .Core import non_library, HasMetadata
+from .Core import non_library, HasMetadata, LibraryElement
 from .Blocks import AbstractBlockProperty
 from .HdlUserExceptions import BlockDefinitionError
 from .HierarchyBlock import Block
@@ -30,7 +30,7 @@ class BlockInterfaceMixin(Block, Generic[MixinBaseType]):
     TODO: what about cases where it's a bit mixed, e.g. HasI2s also needs to register the self.i2s port?
     """
 
-    BaseType = TypeVar("BaseType", bound=HasMetadata)
+    BaseType = TypeVar("BaseType", bound=LibraryElement)
 
     @classmethod
     @override