Test smaract

.vscode/settings.json

@@ -1,2 +1,3 @@
 {
+    "julia.environmentPath": "c:\\Users\\nanol\\Documents\\GitHub\\MicroscopeControl.jl"
 }

Project.toml

@@ -20,7 +20,7 @@ Revise = "295af30f-e4ad-537b-8983-00126c2a3abe"
 Statistics = "10745b16-79ce-11e8-11f9-7d13ad32a3b2"
 
 [sources]
-DAQmx = {url = "https://github.com/LidkeLab/DAQmx.jl.git"}
+DAQmx = {rev = "main", url = "https://github.com/LidkeLab/DAQmx.jl.git"}
 
 [compat]
 CEnum = "0.5.0"

dev/Project.toml

@@ -1,3 +1,6 @@
 [deps]
 MicroscopeControl = "aa70d9ae-4a1e-49fd-870a-8ccfd99f4c3e"
 Revise = "295af30f-e4ad-537b-8983-00126c2a3abe"
+
+[sources]
+MicroscopeControl = {path = "C:\\Users\\sheng\\.julia\\dev\\MicroscopeControl"}

dev/test_fpga.jl

@@ -0,0 +1,46 @@
+using Revise
+using MicroscopeControl
+using MicroscopeControl.HardwareImplementations.XEM_DAC
+
+
+
+fpga = XEM_dac()
+#fpga.xem.bitfile = raw"C:\Users\sheng\Documents\Vivado\dac_clk_fp_1\dac_clk_fp_1.runs\impl_1\dac_clk_fp.bit"
+fpga.xem.bitfile = raw"C:\Users\sheng\Documents\Vivado\dac_slowclk\dac_slowclk.runs\impl_1\dac_clk_fp.bit"
+initialize(fpga.xem)
+
+va = -1.0 # voltage for channel A
+vb = 0.2 # voltage for channel B
+vc = 0.2 # voltage for channel C
+vd = -0.2 # voltage for channel D
+
+start(fpga)
+
+setvoltageA(fpga, va)
+setvoltageB(fpga, vb)
+
+stop(fpga)
+
+
+# generate sawtooth wave on channel A and B
+
+voltages = collect(-0.005:0.002:0.005)
+cyclenum = 20
+start(fpga)
+for cycle in 1:cyclenum
+    for v in voltages
+        #setvoltageA(fpga, v)
+        setvoltageB(fpga, v)
+        #setvoltage(daq,t, v)
+        sleep(0.001)
+    end
+end
+stop(fpga)
+
+
+shutdown(fpga.xem)
+
+
+
+
+

dev/test_fpga_eod.jl

@@ -0,0 +1,73 @@
+
+
+using Revise
+using MicroscopeControl
+using MicroscopeControl.HardwareImplementations.XEM_DAC
+
+
+
+
+fpga = XEM_dac()
+#fpga.xem.bitfile = raw"C:\Users\sheng\Documents\Vivado\dac_slowclk_eod\dac_slowclk_eod.runs\dac_eod_dac1280ns.bit"
+fpga.xem.bitfile = raw"C:\Users\sheng\Documents\Vivado\dac_slowclk_eod\dac_slowclk_eod.runs\dac_eod_dac80ns.bit"
+#fpga.xem.bitfile = raw"C:\Users\sheng\Documents\Vivado\dac_slowclk_eod\dac_slowclk_eod.runs\impl_1\dac_eod.bit"
+initialize(fpga.xem)
+
+va = 0.0 # voltage for channel A
+vb = 0.0 # voltage for channel B
+vc = 0.0 # voltage for channel C
+vd = 0.0 # voltage for channel D
+
+va = -0.01
+vb = -0.015
+vc = -0.02
+vd = -0.025
+
+#code = XEM_DAC.volts_to_code(0.0)
+
+setvoltageD(fpga, 0.5)
+
+
+setvoltageAll(fpga, va,vb,vc,vd)
+
+start(fpga)
+
+
+
+
+stop(fpga)
+
+
+# generate sawtooth wave on channel A and B
+
+
+
+
+
+voltages = collect(-0.005:0.002:0.005)
+cyclenum = 20
+start(fpga)
+for cycle in 1:cyclenum
+    for v in voltages
+        #setvoltageA(fpga, v)
+        setvoltageB(fpga, v)
+        #setvoltage(daq,t, v)
+        sleep(0.001)
+    end
+end
+stop(fpga)
+
+
+
+
+shutdown(fpga.xem)
+
+
+
+
+
+
+
+
+
+

dev/test_fpga_loc.jl

@@ -0,0 +1,96 @@
+using Revise
+using MicroscopeControl
+using MicroscopeControl.HardwareImplementations.OK_XEM
+
+
+
+
+fpga = XEM()
+fpga.bitfile = raw"C:\Users\sheng\Documents\Vivado\test_div\test_div.runs\impl_1\normalize_fp.bit"
+initialize(fpga)
+
+
+#----------------------------------------
+# Endpoint Constants
+#----------------------------------------
+const EP_WIREIN_CTRL = 0x00
+const EP_WIREIN_X0   = 0x01
+const EP_WIREIN_X1   = 0x02
+const EP_WIREIN_X2   = 0x03
+
+const EP_WIREOUT_Y0  = 0x20
+const EP_WIREOUT_Y1  = 0x21
+const EP_WIREOUT_ST  = 0x22
+
+#----------------------------------------
+# Control Constants
+#----------------------------------------
+const CTRL_VALID_ON  = UInt32(0x00000001)
+const CTRL_VALID_OFF = UInt32(0x00000000)
+
+#----------------------------------------
+# Helper: convert 32-bit → signed 16-bit
+#----------------------------------------
+function to_int16(x::UInt32)
+    val = x & 0xFFFF              # keep only lower 16 bits
+    return reinterpret(Int16, UInt16(val))
+end
+
+function q14_to_float(x::UInt32)
+    val = to_int16(x)             # signed 16-bit
+    return Float64(val) / 16384   # 2^14 = 16384
+end
+#----------------------------------------
+# One transaction
+#----------------------------------------
+function send_and_read(fpga::XEM, x0::Int16, x1::Int16, x2::Int16)
+    #x0 = Int16(100)
+    #x1 = Int16(200)
+    #x2 = Int16(20)
+
+    setwirein(fpga, EP_WIREIN_X0, UInt32(reinterpret(UInt16, x0)))
+    setwirein(fpga, EP_WIREIN_X1, UInt32(reinterpret(UInt16, x1)))
+    setwirein(fpga, EP_WIREIN_X2, UInt32(reinterpret(UInt16, x2)))
+
+    # Pulse valid_in using constants
+    setwirein(fpga, EP_WIREIN_CTRL, CTRL_VALID_ON)
+    sleep(0.001)
+    setwirein(fpga, EP_WIREIN_CTRL, CTRL_VALID_OFF)
+    sleep(0.0005)
+
+    status = getwireout(fpga, EP_WIREOUT_ST)
+
+
+    y0_raw = getwireout(fpga, EP_WIREOUT_Y0)
+    y1_raw = getwireout(fpga, EP_WIREOUT_Y1)
+
+    y0_q14 = to_int16(y0_raw)
+    y1_q14 = to_int16(y1_raw)
+
+    y0_real = q14_to_float(y0_raw)
+    y1_real = q14_to_float(y1_raw)
+
+    println("INPUT  : x0=$x0 x1=$x1 x2=$x2")
+    println("OUTPUT : y0_raw=0x", string(y0_raw, base=16), " y1_raw=0x", string(y1_raw, base=16))
+    println("OUTPUT : y0_q14=$y0_q14 y1_q14=$y1_q14 ")
+    println("OUTPUT : y0_real=$(round(y0_real, sigdigits=4)) y1_real=$(round(y1_real, sigdigits=4)) (ready=$status)")
+    println("--------------------------------------")
+
+
+
+end
+
+#----------------------------------------
+# Main test
+#----------------------------------------
+
+
+println("Starting normalize_fp test...\n")
+
+send_and_read(fpga, Int16(20),  Int16(50),  Int16(20))
+send_and_read(fpga, Int16(40),  Int16(20),  Int16(70))
+send_and_read(fpga, Int16(10),     Int16(10),     Int16(10))
+
+println("Test completed.")
+
+shutdown(fpga)

dev/test_nidaq.jl

@@ -0,0 +1,42 @@
+using Revise
+using MicroscopeControl
+using MicroscopeControl.HardwareImplementations.NIDAQcard
+
+
+
+
+
+daq = NIdaq() # the type of daq is NIdaq
+
+
+
+
+devs = showdevices(daq)
+channelsAO = showchannels(daq,"AO",devs[1])
+
+t = createtask(daq,"AO",channelsAO[1]) # the type of t is Task
+setvoltage(daq,t, 0.0) # the maximum voltage is 5.0 V.
+
+t1 = createtask(daq,"AO",channelsAO[2]) # the type of t is Task
+setvoltage(daq,t1, -1.0) # the maximum voltage is 5.0 V.
+
+channelsDO = showchannels(daq,"DO",devs[1])
+t2 = createtask(daq,"DO",channelsDO[1]) # the type of t is Task
+
+setvoltage(daq,t2, 1.0) 
+
+deletetask(daq,t2)
+
+voltages = collect(-0.01:0.005:0.01)
+cyclenum = 10
+
+for cycle in 1:cyclenum
+    for v in voltages
+        setvoltage(daq,t, v)
+        sleep(0.1)
+    end
+end
+
+
+deletetask(daq,t)
+

dev/test_okFP.jl

@@ -0,0 +1,92 @@
+
+include("constants_okFP.jl")
+include("functions_okFP.jl")
+
+const okFP = "C:\\Program Files\\Opal Kelly\\FrontPanelUSB\\API\\lib\\x64\\okFrontPanel.dll"
+
+devicehandle = okFrontPanel_Construct()
+num = okFrontPanel_GetDeviceCount(devicehandle)
+if num == 0
+    println("No fpga board found.")
+    return
+end
+
+# find device model and serial number
+fpgalabel = string(okFrontPanel_GetDeviceListModel(devicehandle, 0))
+println("FPGA board found: " * fpgalabel)
+
+buffersize = 128
+serialstring = zeros(UInt8, buffersize)
+okFrontPanel_GetDeviceListSerial(devicehandle, 0, serialstring)
+serialstring = filter(x -> x != 0x00, serialstring)
+
+# open the device
+err = okFrontPanel_OpenBySerial(devicehandle, serialstring)
+if err != ok_ErrorCode(0)
+    println("Failed to open FPGA board: " * string(err))
+    return
+end
+serialnumber = String(serialstring)
+println("FPGA board serial number: " * serialnumber)
+
+# configure the FPGA
+bitfile = raw"C:\Users\sheng\Documents\Vivado\dac_clk_fp_1\dac_clk_fp_1.runs\impl_1\dac_clk_fp.bit"
+err = okFrontPanel_ConfigureFPGA(devicehandle, bitfile)
+if err != ok_ErrorCode(0)
+    println("Failed to configure FPGA: " * string(err))
+    return
+end
+
+
+
+const EP_WIREIN_A = 0x01
+const EP_WIREIN_B = 0x02
+const EP_WIREIN_C = 0x03
+const EP_WIREIN_D = 0x04
+
+const EP_WIREIN_START = 0x05
+const BIT_START = 0x01
+const BIT_STOP = 0x00
+
+const EP_TRIGGEROUT_CYCLEEND = 0x60
+const TRIG_BIT_CYCLEEND = 0x01
+
+# Voltage-to-code helper (adjust for DAC8814 mode)
+function volts_to_code(v::Float64; vmin::Float64=-10.0, vmax::Float64=10.0)
+    if v < vmin || v > vmax
+        error("Voltage $v V out of range for Vmin=$vmin V and Vmax=$vmax V")
+    end
+    return UInt32(round(65535 - ((v - vmin) / (vmax - vmin)) * 65535))
+end
+
+# Main routine
+
+
+# Example voltages
+a = volts_to_code(-0.205)
+b = volts_to_code(0.205)
+c = volts_to_code(0.405)
+d = volts_to_code(-0.405)
+
+# Write voltages
+
+err = okFrontPanel_SetWireInValue(devicehandle, EP_WIREIN_A, a, 0xFFFF)
+err = okFrontPanel_SetWireInValue(devicehandle, EP_WIREIN_B, b, 0xFFFF)
+err = okFrontPanel_SetWireInValue(devicehandle, EP_WIREIN_C, c, 0xFFFF)
+err = okFrontPanel_SetWireInValue(devicehandle, EP_WIREIN_D, d, 0xFFFF)
+err = okFrontPanel_UpdateWireIns(devicehandle)
+
+# start
+err = okFrontPanel_SetWireInValue(devicehandle, EP_WIREIN_START, BIT_START, 0xFFFF)
+err = okFrontPanel_UpdateWireIns(devicehandle)
+# stop
+err = okFrontPanel_SetWireInValue(devicehandle, EP_WIREIN_START, BIT_STOP, 0xFFFF)
+err = okFrontPanel_UpdateWireIns(devicehandle)
+
+#err = okFrontPanel_ActivateTriggerIn(devicehandle, EP_TRIGGERIN_START, TRIG_BIT_START)
+
+#err = okFrontPanel_UpdateTriggerOuts(devicehandle)
+
+#iscycleend = okFrontPanel_IsTriggered(devicehandle, EP_TRIGGEROUT_CYCLEEND, TRIG_BIT_CYCLEEND)
+
+err = okFrontPanel_Destruct(devicehandle)

dev/test_smaract_stage.jl

@@ -0,0 +1,18 @@
+using Pkg
+Pkg.activate("C:\\Users\\nanol\\.julia\\dev\\MicroscopeControl.jl")
+using MicroscopeControl
+
+stage = MCS2Stage(
+    stagelabel = "SmarAct MCS2",
+    n_channels = 3,
+    channel_ids = Int32[0, 1, 2],
+)
+
+initialize(stage)
+
+# move_um!(stage, [10.0, 5.0 ,0.0]) 
+
+stage.range_x = (-20_000.0, 20_000.0)   # µm, since these fields are in micrometres, software limits only, not hardware limits. The hardware limits are in the device's firmware and cannot be changed from software.
+stage.range_y = (-20_000.0, 20_000.0)
+
+MicroscopeControl.HardwareInterfaces.StageInterface.gui(stage)