Mcl86jr correctness fixes - #55

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mx-shift wants to merge 8 commits into

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mx-shift:mcl86jr-fixes

Commits on May 10, 2026

BIU: ack HALT immediately without running a bus cycle
mx-shift
committed
801c16c
BIU: stage CS register update so it commits atomically with pfq_addr_in
mx-shift
committed
ae1b2ef
Add microcode assembler
mx-shift
committed
729eeb6
V5 microcode: STORE/RESTORE_SEG_PREFIX use r2 scratch, not AF flag
mx-shift
committed
21663c6
V6 microcode: don't skip INT poll for non-SS segment loads
mx-shift
committed
060bf4e
BIU: proper 8086 offset-wrap on word-read byte-2 address
mx-shift
committed
063896e

Commits on May 19, 2026

V7 microcode + eu.v: IRET interrupt-recognition fix
mx-shift
committed
5c3c7e7

Commits on May 21, 2026

V8 microcode: AAM/AAD flags from AL, not full AX
mx-shift
committed
ff88e39