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The K-specialized casts assume default padded scale strides, so caller-provided pitches put scale values in the wrong rows. Use those specializations only when both strides match their constants. Other layouts use the existing runtime-stride kernel. Cover custom pitches, default layouts, and the runtime-width path with GPU regressions. Signed-off-by: bvolpato <brunocvcunha@gmail.com>
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Description
Honor caller-provided scale strides in bidirectional BF16-to-MXFP8 casts. The 2048- and 4096-column kernel specializations bake in TE's default padded scale strides. When an output tensor supplies a larger rowwise or columnwise pitch, scale values land in the wrong logical rows even though the FP8 payload is correct.
For example, BF16 input shaped
(64, 2048)with unswizzled scale shapes(64, 68)and(2, 2064)reproduces the corruption. Use the K-specialized kernel only when both strides match its constants. Other layouts use the existing runtime-stride kernel.Related to #3710.
Type of change
Changes
Validation
Built the common library and PyTorch extension for an RTX 5070 Ti (SM120), using CUDA 13.2 and PyTorch 2.12.1 with NCCL EP and CuTeDSL disabled. Verified the imported libraries came from the tested checkout. The regression fails before the fix and passes afterward. Direct CUDA launcher checks, Compute Sanitizer memcheck, scoped pre-commit, C++ L0 lint, and the license check passed.
Rerun the focused check with:
The full L0 runtime and JAX suites were not run.
Checklist: