Merge to tag jdk-28+18

.github/workflows/build-windows.yml

@@ -147,7 +147,7 @@ jobs:
         run: |
           # Run Visual Studio Installer
           '/c/Program Files (x86)/Microsoft Visual Studio/Installer/vs_installer.exe' \
-            modify --quiet --installPath 'C:\Program Files\Microsoft Visual Studio\2022\Enterprise' \
+            modify --quiet --installPath 'C:\Program Files\Microsoft Visual Studio\18\Enterprise' \
             --add Microsoft.VisualStudio.Component.VC.${{ inputs.msvc-toolset-version }}.ARM64
         if: ${{ ( inputs.architecture == 'ARM64') && (steps.toolchain-check-arm64.outputs.toolchain-installed != 'true') }}
 

.github/workflows/main.yml

@@ -362,7 +362,7 @@ jobs:
       platform: macos-x64
       runs-on: 'macos-15-intel'
       xcode-toolset-version: '16.4'
-      configure-arguments: ${{ github.event.inputs.configure-arguments }}
+      configure-arguments: ${{ github.event.inputs.configure-arguments }} --enable-deprecated-ports
       make-arguments: ${{ github.event.inputs.make-arguments }}
       dry-run: ${{ needs.prepare.outputs.dry-run == 'true' }}
     if: needs.prepare.outputs.macos-x64 == 'true'
@@ -402,7 +402,7 @@ jobs:
       platform: windows-aarch64
       runs-on: windows-11-arm
       architecture: 'ARM64'
-      msvc-toolset-version: '14.44'
+      msvc-toolset-version: '14.51'
       configure-arguments: ${{ github.event.inputs.configure-arguments }}
       make-arguments: ${{ github.event.inputs.make-arguments }}
       dry-run: ${{ needs.prepare.outputs.dry-run == 'true' }}

make/conf/github-actions.conf

@@ -29,29 +29,29 @@ GTEST_VERSION=1.14.0
 JTREG_VERSION=8.3+1
 
 LINUX_X64_BOOT_JDK_EXT=tar.gz
-LINUX_X64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-26.0.1/sapmachine-jdk-26.0.1_linux-x64_bin.tar.gz
-LINUX_X64_BOOT_JDK_SHA256=4422a642da9764419477a80bea1d614391c40b71060f0de1610467d4c70807a0
+LINUX_X64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-27/sapmachine-jdk-27_linux-x64_bin.tar.gz
+LINUX_X64_BOOT_JDK_SHA256=de400f5991c440d9a454e8d6470cec398ed5cf13277ba890d519d8c661bd8194
 
 LINUX_AARCH64_BOOT_JDK_EXT=tar.gz
-LINUX_AARCH64_BOOT_JDK_URL=https://download.java.net/java/GA/jdk26/c3cc523845074aa0af4f5e1e1ed4151d/35/GPL/openjdk-26_linux-aarch64_bin.tar.gz
-LINUX_AARCH64_BOOT_JDK_SHA256=403ccf451e88d0be9e1dec129fcb9318de9752121e0eb92dfa9a8cf06f249007
+LINUX_AARCH64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-27/sapmachine-jdk-27_linux-aarch64_bin.tar.gz
+LINUX_AARCH64_BOOT_JDK_SHA256=cee720ad293ade5c13d2a8f286e7c2f4a58b09c3623b6c5c44757b22c7f3f58b
 
 ALPINE_LINUX_X64_BOOT_JDK_EXT=tar.gz
-ALPINE_LINUX_X64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-26.0.1/sapmachine-jdk-26.0.1_linux-x64-musl_bin.tar.gz
-ALPINE_LINUX_X64_BOOT_JDK_SHA256=58dad03eaf3ec5d40bc2f94d8c1bd5f6e47c650d2d6b52fe3572926285f62e04
+ALPINE_LINUX_X64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-27/sapmachine-jdk-27_linux-x64-musl_bin.tar.gz
+ALPINE_LINUX_X64_BOOT_JDK_SHA256=b6255ecb0075edf69d3b57fb57d3b29c231fc7aad36c49b7d7594646c3c0754f
 
 MACOS_AARCH64_BOOT_JDK_EXT=tar.gz
-MACOS_AARCH64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-26.0.1/sapmachine-jdk-26.0.1_macos-aarch64_bin.tar.gz
-MACOS_AARCH64_BOOT_JDK_SHA256=3663faab53b08e20c87112166bae3399340ead434d8e3a58cbb2a28ef1e0c584
+MACOS_AARCH64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-27/sapmachine-jdk-27_macos-aarch64_bin.tar.gz
+MACOS_AARCH64_BOOT_JDK_SHA256=d11f398a0f518e238daae90db03a802c13a105288385c6c4e139a7de487ce56b
 
 MACOS_X64_BOOT_JDK_EXT=tar.gz
-MACOS_X64_BOOT_JDK_URL=https://download.java.net/java/GA/jdk26/c3cc523845074aa0af4f5e1e1ed4151d/35/GPL/openjdk-26_macos-x64_bin.tar.gz
-MACOS_X64_BOOT_JDK_SHA256=8642b89d889c14ede2c446fd5bbe3621c8a3082e3df02013fd1658e39f52929a
+MACOS_X64_BOOT_JDK_URL=https://github.com/adoptium/temurin27-binaries/releases/download/jdk-27%2B35-ea-beta/OpenJDK27U-jdk_x64_mac_hotspot_27_35-ea.tar.gz
+MACOS_X64_BOOT_JDK_SHA256=dba58de67ddff845fef0654d439fba39cf0185d3f6c1c6e323de33ced9e72018
 
 WINDOWS_X64_BOOT_JDK_EXT=zip
-WINDOWS_X64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-26.0.1/sapmachine-jdk-26.0.1_windows-x64_bin.zip
-WINDOWS_X64_BOOT_JDK_SHA256=1b7ff2fe4bb201047a7e43b83c318b9e0bf53bd8a9ea8e8ac95df2917ff0cbd8
+WINDOWS_X64_BOOT_JDK_URL=https://github.com/SAP/SapMachine/releases/download/sapmachine-27/sapmachine-jdk-27_windows-x64_bin.zip
+WINDOWS_X64_BOOT_JDK_SHA256=2571e5596ab92a9f43d69f38f3f2ad23cdc2baf91bc4b4b4d80cfde1a25a4f2f
 
 WINDOWS_AARCH64_BOOT_JDK_EXT=zip
-WINDOWS_AARCH64_BOOT_JDK_URL=https://github.com/adoptium/temurin26-binaries/releases/download/jdk-26%2B35-ea-beta/OpenJDK26U-jdk_aarch64_windows_hotspot_26_35-ea.zip
-WINDOWS_AARCH64_BOOT_JDK_SHA256=4892cd9714e222947de1a7415a696f43adf691560522dc5858c0a8af070912c0
+WINDOWS_AARCH64_BOOT_JDK_URL=https://github.com/adoptium/temurin27-binaries/releases/download/jdk-27%2B35-ea-beta/OpenJDK27U-jdk_aarch64_windows_hotspot_27_35-ea.zip
+WINDOWS_AARCH64_BOOT_JDK_SHA256=0bcfb220eb885776da39cc6de50898f62fe34865e48c49d9e2a98070fe4049b5

make/conf/jib-profiles.js

@@ -387,7 +387,7 @@ var getJibProfilesCommon = function (input, data) {
         };
     };
 
-    common.boot_jdk_version = "26";
+    common.boot_jdk_version = "27";
     common.boot_jdk_build_number = "35";
     common.boot_jdk_home = input.get("boot_jdk", "install_path") + "/jdk-"
         + common.boot_jdk_version

make/conf/version-numbers.conf

@@ -37,6 +37,6 @@ DEFAULT_VERSION_DATE=2027-03-23
 DEFAULT_VERSION_CLASSFILE_MAJOR=72  # "`$EXPR $DEFAULT_VERSION_FEATURE + 44`"
 DEFAULT_VERSION_CLASSFILE_MINOR=0
 DEFAULT_VERSION_DOCS_API_SINCE=11
-DEFAULT_ACCEPTABLE_BOOT_VERSIONS="26 27 28"
+DEFAULT_ACCEPTABLE_BOOT_VERSIONS="27 28"
 DEFAULT_JDK_SOURCE_TARGET_VERSION=28
 DEFAULT_PROMOTED_VERSION_PRE=ea

src/hotspot/cpu/aarch64/aarch64.ad

@@ -1,7 +1,7 @@
 //
 // Copyright (c) 2003, 2026, Oracle and/or its affiliates. All rights reserved.
 // Copyright (c) 2014, 2024, Red Hat, Inc. All rights reserved.
-// Copyright 2025 Arm Limited and/or its affiliates.
+// Copyright 2025, 2026 Arm Limited and/or its affiliates.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -546,6 +546,9 @@ reg_class int_r3_reg(R3);
 // Singleton class for R4 int register
 reg_class int_r4_reg(R4);
 
+// Singleton class for R5 int register
+reg_class int_r5_reg(R5);
+
 // Singleton class for R31 int register
 reg_class int_r31_reg(R31);
 
@@ -4914,6 +4917,18 @@ operand iRegI_R4()
 %}
 
 
+// Register R5 only
+operand iRegI_R5()
+%{
+  constraint(ALLOC_IN_RC(int_r5_reg));
+  match(RegI);
+  match(iRegINoSp);
+  op_cost(0);
+  format %{ %}
+  interface(REG_INTER);
+%}
+
+
 // Pointer Register Operands
 // Narrow Pointer Register
 operand iRegN()
@@ -16143,18 +16158,50 @@ instruct stringU_indexof_char_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
   ins_pipe(pipe_class_memory);
 %}
 
-instruct string_equalsL(iRegP_R1 str1, iRegP_R3 str2, iRegI_R4 cnt,
-                        iRegI_R0 result, rFlagsReg cr)
+instruct string_equalsL_sve(
+    iRegP_R1   str1,      // str1 (kill)
+    iRegP_R3   str2,      // str2 (kill)
+    iRegINoSp   cnt,       // int length
+    iRegINoSp   result,    // boolean
+    vecA ztmp1, vecA ztmp2, // SVE z registers
+    pRegGov pg, pReg pdata, // SVE predicate registers
+    rFlagsReg  cr)
+%{
+  predicate(UseSVE > 0 && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
+  match(Set result (StrEquals (Binary str1 str2) cnt));
+  effect(USE_KILL str1, USE_KILL str2, USE cnt, TEMP ztmp1, TEMP ztmp2, TEMP pg, TEMP pdata, KILL cr);
+
+  format %{ "String Equals $str1,$str2,$cnt -> $result" %}
+  ins_encode %{
+    // Count is in 8-bit bytes; non-Compact chars are 16 bits.
+    __ string_equals_sve($str1$$Register, $str2$$Register,
+                     $result$$Register, $cnt$$Register,
+                     $ztmp1$$FloatRegister,
+                     $ztmp2$$FloatRegister, $pg$$PRegister,
+                     $pdata$$PRegister);
+  %}
+  ins_pipe(pipe_class_memory);
+%}
+
+instruct string_equalsL(
+    iRegP_R1   str1,      // str1 (kill)
+    iRegP_R3   str2,      // str2 (kill)
+    iRegI_R4   cnt,       // int length (kill)
+    iRegI_R0   result,    // boolean
+    iRegINoSp  str1_hi,     // temp: str1 high 8B
+    iRegINoSp  str2_hi,     // temp: str2 high 8B (reused as shift amount in SMALL)
+    rFlagsReg  cr)
 %{
-  predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
+  predicate(UseSVE == 0 && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
   match(Set result (StrEquals (Binary str1 str2) cnt));
-  effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
+  effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP str1_hi, TEMP str2_hi, KILL cr);
 
   format %{ "String Equals $str1,$str2,$cnt -> $result" %}
   ins_encode %{
     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
     __ string_equals($str1$$Register, $str2$$Register,
-                     $result$$Register, $cnt$$Register);
+                     $result$$Register, $cnt$$Register,
+                     $str1_hi$$Register, $str2_hi$$Register);
   %}
   ins_pipe(pipe_class_memory);
 %}
@@ -16210,19 +16257,22 @@ instruct array_equalsC(iRegP_R1 ary1, iRegP_R2 ary2, iRegI_R0 result,
 %}
 
 instruct arrays_hashcode(iRegP_R1 ary, iRegI_R2 cnt, iRegI_R0 result, immI basic_type,
+                         iRegI_R3 blocks, iRegI_R4 tail, iRegI_R5 sum,
                          vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2, vRegD_V3 vtmp3,
                          vRegD_V4 vtmp4, vRegD_V5 vtmp5, vRegD_V6 vtmp6, vRegD_V7 vtmp7,
                          vRegD_V12 vtmp8, vRegD_V13 vtmp9, rFlagsReg cr)
 %{
   match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
-  effect(TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5, TEMP vtmp6,
+  effect(TEMP blocks, TEMP tail, TEMP sum,
+         TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5, TEMP vtmp6,
          TEMP vtmp7, TEMP vtmp8, TEMP vtmp9, USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
 
   format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result   // KILL all" %}
   ins_encode %{
     address tpc = __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
-                                     $vtmp3$$FloatRegister, $vtmp2$$FloatRegister,
-                                     $vtmp1$$FloatRegister, $vtmp0$$FloatRegister,
+                                     $blocks$$Register, $tail$$Register, $sum$$Register,
+                                     $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
+                                     $vtmp2$$FloatRegister, $vtmp3$$FloatRegister,
                                      $vtmp4$$FloatRegister, $vtmp5$$FloatRegister,
                                      $vtmp6$$FloatRegister, $vtmp7$$FloatRegister,
                                      $vtmp8$$FloatRegister, $vtmp9$$FloatRegister,

src/hotspot/cpu/aarch64/aarch64_vector.ad

@@ -6883,14 +6883,14 @@ instruct vmask_lasttrue_neon(iRegINoSp dst, vReg src) %{
   ins_pipe(pipe_slow);
 %}
 
-instruct vmask_lasttrue_sve(iRegINoSp dst, pReg src, pReg ptmp) %{
+instruct vmask_lasttrue_sve(iRegINoSp dst, pRegGov src, vReg vtmp, rFlagsReg cr) %{
   predicate(UseSVE > 0);
   match(Set dst (VectorMaskLastTrue src));
-  effect(TEMP ptmp);
-  format %{ "vmask_lasttrue_sve $dst, $src\t# KILL $ptmp" %}
+  effect(TEMP vtmp, KILL cr);
+  format %{ "vmask_lasttrue_sve $dst, $src\t# KILL $vtmp, cr" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src);
-    __ sve_vmask_lasttrue($dst$$Register, bt, $src$$PRegister, $ptmp$$PRegister);
+    __ sve_vmask_lasttrue($dst$$Register, bt, $src$$PRegister, $vtmp$$FloatRegister);
   %}
   ins_pipe(pipe_slow);
 %}

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -4584,14 +4584,14 @@ instruct vmask_lasttrue_neon(iRegINoSp dst, vReg src) %{
   ins_pipe(pipe_slow);
 %}
 
-instruct vmask_lasttrue_sve(iRegINoSp dst, pReg src, pReg ptmp) %{
+instruct vmask_lasttrue_sve(iRegINoSp dst, pRegGov src, vReg vtmp, rFlagsReg cr) %{
   predicate(UseSVE > 0);
   match(Set dst (VectorMaskLastTrue src));
-  effect(TEMP ptmp);
-  format %{ "vmask_lasttrue_sve $dst, $src\t# KILL $ptmp" %}
+  effect(TEMP vtmp, KILL cr);
+  format %{ "vmask_lasttrue_sve $dst, $src\t# KILL $vtmp, cr" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src);
-    __ sve_vmask_lasttrue($dst$$Register, bt, $src$$PRegister, $ptmp$$PRegister);
+    __ sve_vmask_lasttrue($dst$$Register, bt, $src$$PRegister, $vtmp$$FloatRegister);
   %}
   ins_pipe(pipe_slow);
 %}

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

@@ -72,11 +72,12 @@ void C2_MacroAssembler::entry_barrier() {
 
 // jdk.internal.util.ArraysSupport.vectorizedHashCode
 address C2_MacroAssembler::arrays_hashcode(Register ary, Register cnt, Register result,
-                                           FloatRegister vdata0, FloatRegister vdata1,
-                                           FloatRegister vdata2, FloatRegister vdata3,
-                                           FloatRegister vmul0, FloatRegister vmul1,
-                                           FloatRegister vmul2, FloatRegister vmul3,
-                                           FloatRegister vpow, FloatRegister vpowm,
+                                           Register blocks, Register tail, Register sum,
+                                           FloatRegister v_block0, FloatRegister v_block1,
+                                           FloatRegister v_block2, FloatRegister v_block3,
+                                           FloatRegister v_p0, FloatRegister v_p1,
+                                           FloatRegister v_p2, FloatRegister v_p3,
+                                           FloatRegister v_input1, FloatRegister v_input2,
                                            BasicType eltype) {
   ARRAYS_HASHCODE_REGISTERS;
 
@@ -116,9 +117,8 @@ address C2_MacroAssembler::arrays_hashcode(Register ary, Register cnt, Register
     ShouldNotReachHere();
   }
 
-  // large_arrays_hashcode(T_INT) performs worse than the scalar loop below when the Neon loop
-  // implemented by the stub executes just once. Call the stub only if at least two iterations will
-  // be executed.
+  // large_arrays_hashcode(T_INT) uses SIMD for >= 8 elements.
+  // For lower lengths we use an unrolled loop.
   const size_t large_threshold = eltype == T_INT ? vf * 2 : vf;
   cmpw(cnt, large_threshold);
   br(Assembler::HS, LARGE);
@@ -1129,6 +1129,43 @@ void C2_MacroAssembler::stringL_indexof_char(Register str1, Register cnt1,
   BIND(DONE);
 }
 
+void C2_MacroAssembler::string_equals_sve(Register a1, Register a2,
+                                      Register result, Register cnt1,
+                                      FloatRegister ztmp1, FloatRegister ztmp2,
+                                      PRegister pg, PRegister pdata) {
+  Label LOOP, TAIL, END;
+  Register vec_len = rscratch1;
+  Register tmp_cnt1     = rscratch2;
+  sve_cntb(vec_len);
+  // Keep original cnt1 for the len <= VL tail decision.
+  // If length(cnt1) <= VL go to the tail
+  subs(tmp_cnt1, cnt1, vec_len);
+  br(Assembler::LE, TAIL);
+  sve_ptrue(pg, B);
+  bind(LOOP);
+    sve_ld1b(ztmp1, B, pg, Address(a1));
+    sve_ld1b(ztmp2, B, pg, Address(a2));
+    add(a1, a1, vec_len);
+    add(a2, a2, vec_len);
+    sve_cmp(Assembler::NE, pdata, B, pg, ztmp1, ztmp2);
+    br(Assembler::NE, END);
+    subs(tmp_cnt1, tmp_cnt1, vec_len);
+    br(Assembler::HI, LOOP);
+  // Final overlapped full-VL compare.
+  sve_ld1b(ztmp1, B, pg, Address(a1, tmp_cnt1));
+  sve_ld1b(ztmp2, B, pg, Address(a2, tmp_cnt1));
+  sve_cmp(Assembler::NE, pdata, B, pg, ztmp1, ztmp2);
+  b(END);
+
+  bind(TAIL);
+    sve_whilelt(pg, B, zr, cnt1);
+    sve_ld1b(ztmp1, B, pg, Address(a1));
+    sve_ld1b(ztmp2, B, pg, Address(a2));
+    sve_cmp(Assembler::NE, pdata, B, pg, ztmp1, ztmp2);
+  bind(END);
+    cset(result, Assembler::EQ);
+}
+
 // Compare strings.
 void C2_MacroAssembler::string_compare(Register str1, Register str2,
     Register cnt1, Register cnt2, Register result, Register tmp1, Register tmp2,
@@ -1567,13 +1604,18 @@ void C2_MacroAssembler::sve_compare(PRegister pd, BasicType bt, PRegister pg,
 }
 
 // Get index of the last mask lane that is set
-void C2_MacroAssembler::sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp) {
+// Clobbers: rflags
+void C2_MacroAssembler::sve_vmask_lasttrue(Register dst, BasicType bt,
+                                           PRegister src, FloatRegister vtmp) {
   SIMD_RegVariant size = elemType_to_regVariant(bt);
-  sve_rev(ptmp, size, src);
-  sve_brkb(ptmp, ptrue, ptmp, false);
-  sve_cntp(dst, size, ptrue, ptmp);
-  movw(rscratch1, MaxVectorSize / type2aelembytes(bt) - 1);
-  subw(dst, rscratch1, dst);
+  // vtmp = 0, 1, 2, ...
+  sve_index(vtmp, size, 0, 1);
+  // dst = last true or the highest-numbered element if src is all false
+  sve_lastb(dst, size, src, vtmp);
+  // Zero flag = 1 iff no active lane
+  sve_ptest(ptrue, src);
+  // active: keep; else -1
+  csinvw(dst, dst, zr, Assembler::NE);
 }
 
 // Extend integer vector src to dst with the same lane count

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

@@ -80,16 +80,20 @@
   void entry_barrier();
 
   // jdk.internal.util.ArraysSupport.vectorizedHashCode
-  address arrays_hashcode(Register ary, Register cnt, Register result, FloatRegister vdata0,
-                          FloatRegister vdata1, FloatRegister vdata2, FloatRegister vdata3,
-                          FloatRegister vmul0, FloatRegister vmul1, FloatRegister vmul2,
-                          FloatRegister vmul3, FloatRegister vpow, FloatRegister vpowm,
+  address arrays_hashcode(Register ary, Register cnt, Register result, Register blocks,
+                          Register tail, Register sum, FloatRegister v_block0, FloatRegister v_block1,
+                          FloatRegister v_block2, FloatRegister v_block3, FloatRegister v_p0, FloatRegister v_p1,
+                          FloatRegister v_p2, FloatRegister v_p3, FloatRegister v_input1, FloatRegister v_input2,
                           BasicType eltype);
 
   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
   void fast_lock(Register object, Register box, Register t1, Register t2, Register t3);
   void fast_unlock(Register object, Register box, Register t1, Register t2, Register t3);
 
+  void string_equals_sve(Register a1, Register a2, Register result, Register cnt1,
+                           FloatRegister ztmp1, FloatRegister ztmp2,
+                           PRegister pgtmp, PRegister ptmp);
+
   void string_compare(Register str1, Register str2,
                       Register cnt1, Register cnt2, Register result,
                       Register tmp1, Register tmp2, FloatRegister vtmp1,
@@ -144,7 +148,7 @@
   void sve_compare(PRegister pd, BasicType bt, PRegister pg,
                    FloatRegister zn, FloatRegister zm, Condition cond);
 
-  void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
+  void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, FloatRegister vtmp);
 
   // Vector cast
   void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,

src/hotspot/cpu/aarch64/c2_globals_aarch64.hpp

@@ -61,7 +61,6 @@ define_pd_global(intx, RegisterCostAreaRatio,        16000);
 define_pd_global(bool, OptoPeephole,                 false);
 define_pd_global(bool, UseCISCSpill,                 false);
 define_pd_global(bool, OptoScheduling,               false);
-define_pd_global(bool, OptoBundling,                 false);
 define_pd_global(bool, OptoRegScheduling,            false);
 define_pd_global(bool, SuperWordLoopUnrollAnalysis,  true);
 define_pd_global(uint, SuperWordStoreToLoadForwardingFailureDetection, 8);

src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp

@@ -445,7 +445,7 @@ void G1BarrierSetAssembler::oop_store_at(MacroAssembler* masm, DecoratorSet deco
 #undef __
 #define __ ce->masm()->
 
-void G1BarrierSetAssembler::gen_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStub* stub) {
+void G1BarrierSetAssembler::gen_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStubC1* stub) {
   G1BarrierSetC1* bs = (G1BarrierSetC1*)BarrierSet::barrier_set()->barrier_set_c1();
   // At this point we know that marking is in progress.
   // If do_load() is true then we have to emit the