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gt2n: port bp_uno #243

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16 changes: 16 additions & 0 deletions designs/gt2n/bp_processor/BUILD.bazel
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package(default_visibility = ["//designs/gt2n/bp_processor:__subpackages__"])

filegroup(
name = "macros",
srcs = ["macros.v"],
)

filegroup(
name = "sram_lefs",
srcs = glob(["sram/lef/*.lef"]),
)

filegroup(
name = "sram_libs",
srcs = glob(["sram/lib/*.lib"]),
)
33 changes: 33 additions & 0 deletions designs/gt2n/bp_processor/bp_uno/BUILD.bazel
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load("//:defs.bzl", "hightide_design")
load("//designs/src/bp_processor:defs.bzl", "BP_COMMON_ARGS")

_ARGS = dict(BP_COMMON_ARGS)

_ARGS.update({
# RTLMP auto macro placement, no hand-placed grid.
# Auto-sized via CORE_UTILIZATION rather than a fixed DIE_AREA/CORE_AREA.
"CORE_UTILIZATION": "35",
"PLACE_PINS_ARGS": "-min_distance 20 -min_distance_in_tracks",
"MACRO_PLACE_HALO": "8 8",
"PLACE_DENSITY": "0.42",
"MAX_ROUTING_LAYER": "M11",
"MIN_CLK_ROUTING_LAYER": "M4",
"TNS_END_PERCENT": "100",
"NUM_CORES": "16",
})

hightide_design(
name = "bp_processor",
platform = "gt2n",
verilog_files = [
"//designs/src/bp_processor:rtl",
"//designs/gt2n/bp_processor:macros",
],
sources = {
"SDC_FILE": [":constraint.sdc"],
"ADDITIONAL_LEFS": ["//designs/gt2n/bp_processor:sram_lefs"],
"ADDITIONAL_LIBS": ["//designs/gt2n/bp_processor:sram_libs"],
},
arguments = _ARGS,
stage_data = {"synth": ["//designs/src/bp_processor:rtl_data"]},
)
15 changes: 15 additions & 0 deletions designs/gt2n/bp_processor/bp_uno/constraint.sdc
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current_design bp_processor

set clk_name CLK
set clk_port_name clk_i
set clk_period 4628
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
235 changes: 235 additions & 0 deletions designs/gt2n/bp_processor/macros.v
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// Auto-generated by designs/src/bp_processor/dev/gen_macros_v.py — do not edit.
//
// Large memories (listed below) bind to bsg_fakeram-generated
// fakeram_DxW_1rw macros via the rw0_* pin convention. Everything else
// falls through to a behavioural register array (synthesises to FFs).

module bsg_mem_1rw_sync_synth (
clk_i,
v_i,
reset_i,
data_i,
addr_i,
w_i,
data_o
);
parameter width_p = 0;
parameter els_p = 0;
parameter latch_last_read_p = 0;
parameter addr_width_lp = ((els_p == 1) || (els_p == 0) ? 1 : $clog2(els_p));
parameter verbose_p = 1;
input clk_i;
input v_i;
input reset_i;
input [(width_p < 1 ? 0 : width_p - 1):0] data_i;
input [addr_width_lp - 1:0] addr_i;
input w_i;
output wire [(width_p < 1 ? 0 : width_p - 1):0] data_o;
wire unused = reset_i;
generate
if ((width_p == 0) || (els_p == 0)) begin : z
wire unused0 = &{clk_i, v_i, data_i, addr_i, w_i};
assign data_o = 1'sb0;
end
else if ((els_p == 512) && (width_p == 64)) begin : fakeram_512x64
fakeram_512x64_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in({64{w_i}}),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 64) && (width_p == 184)) begin : fakeram_64x184
fakeram_64x184_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in({184{w_i}}),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 512) && (width_p == 8)) begin : fakeram_512x8
fakeram_512x8_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in({8{w_i}}),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 64) && (width_p == 50)) begin : fakeram_64x50
fakeram_64x50_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in({50{w_i}}),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 32) && (width_p == 48)) begin : fakeram_32x48
fakeram_32x48_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in({48{w_i}}),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 128) && (width_p == 8)) begin : fakeram_128x8
fakeram_128x8_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in({8{w_i}}),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else begin : nz
reg [addr_width_lp - 1:0] addr_r;
reg [width_p - 1:0] mem [els_p - 1:0];
wire read_en;
wire [width_p - 1:0] data_out;
wire [addr_width_lp - 1:0] addr_li = (els_p > 0 ? addr_i : {addr_width_lp {1'sb0}});
assign read_en = v_i & ~w_i;
assign data_out = mem[addr_r];
always @(posedge clk_i)
if (read_en)
addr_r <= addr_li;
else
addr_r <= 1'sbx;
assign data_o = data_out;
always @(posedge clk_i)
if (v_i & w_i)
mem[addr_li] <= data_i;
end
endgenerate
endmodule

module bsg_mem_1rw_sync_mask_write_bit_synth (
clk_i,
reset_i,
data_i,
addr_i,
v_i,
w_mask_i,
w_i,
data_o
);
parameter width_p = 0;
parameter els_p = 0;
parameter latch_last_read_p = 0;
parameter addr_width_lp = ((els_p == 1) || (els_p == 0) ? 1 : $clog2(els_p));
parameter verbose_p = 1;
input clk_i;
input reset_i;
input [(width_p < 1 ? 0 : width_p - 1):0] data_i;
input [addr_width_lp - 1:0] addr_i;
input v_i;
input [(width_p < 1 ? 0 : width_p - 1):0] w_mask_i;
input w_i;
output wire [(width_p < 1 ? 0 : width_p - 1):0] data_o;
wire unused = reset_i;
generate
if ((width_p == 0) || (els_p == 0)) begin : z
wire unused0 = &{clk_i, data_i, addr_i, v_i, w_mask_i, w_i};
assign data_o = 1'sb0;
end
else if ((els_p == 512) && (width_p == 64)) begin : fakeram_512x64
fakeram_512x64_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in(w_mask_i),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 64) && (width_p == 184)) begin : fakeram_64x184
fakeram_64x184_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in(w_mask_i),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 512) && (width_p == 8)) begin : fakeram_512x8
fakeram_512x8_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in(w_mask_i),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 64) && (width_p == 50)) begin : fakeram_64x50
fakeram_64x50_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in(w_mask_i),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 32) && (width_p == 48)) begin : fakeram_32x48
fakeram_32x48_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in(w_mask_i),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else if ((els_p == 128) && (width_p == 8)) begin : fakeram_128x8
fakeram_128x8_1rw mem (
.rw0_clk(clk_i),
.rw0_ce_in(v_i),
.rw0_we_in(w_i),
.rw0_wmask_in(w_mask_i),
.rw0_addr_in(addr_i),
.rw0_wd_in(data_i),
.rw0_rd_out(data_o)
);
end
else begin : nz
reg [addr_width_lp - 1:0] addr_r;
reg [width_p - 1:0] mem [els_p - 1:0];
wire read_en;
wire [width_p - 1:0] data_out;
wire [addr_width_lp - 1:0] addr_li = (els_p > 0 ? addr_i : {addr_width_lp {1'sb0}});
assign read_en = v_i & ~w_i;
assign data_out = mem[addr_r];
always @(posedge clk_i)
if (read_en)
addr_r <= addr_li;
else
addr_r <= 1'sbx;
assign data_o = data_out;
always @(posedge clk_i)
if (v_i & w_i)
mem[addr_li] <= data_i;
end
endgenerate
endmodule
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