6502-ACE

An AC6502 retro-style 8-bit computer based on the 65C02 microprocessor.

📖 Guide: AC6502 Documentation — the user's and programmer's guide for the whole family. Start with Your ACE, the tour of this board.

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Table of Contents

• Overview
• Architecture
• Systems
• Software
• Hardware
  • ACE Board
    • Revision History
  • ACE CF Adapter
  • ACE RAM Patch
• Firmware
  • AB Controller
• CAD
• Production
• Schematics
• Checking the schematics
• Libraries
• Bill of Materials
  • ACE Board
  • ACE CF Adapter
  • ACE RAM Patch
• License

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Overview

The AC6502 ecosystem is a family of open-source, 65C02-based computers sharing a common architecture, memory map, and BIOS. Each computer in the family is purpose-built for a different use case but runs the same software and firmware.

The ACE (All-in-one Computer Experience) is a complete, self-contained 65C02 computer on a single PCB. It integrates everything found across the COB's modular cards — CPU, memory, video, audio, storage, serial, GPIO, RTC, and keyboard controller — onto one board, delivering the full experience without a backplane or expansion cards.

Architecture

All AC6502 computers share:

• CPU: 65C02 (or accurate emulation)
• Memory: 32KB RAM + 32KB ROM, with optional banked RAM expansion
• Memory Map: Standardized across the ecosystem — zero page, stack, I/O space ($8000–$9FFF), system ROM, and interrupt vectors at $FFFA–$FFFF
• Bus: 16-bit address bus, 8-bit bidirectional data bus, standard 65C02 control signals (RW, PHI2, RESET, IRQ, NMI, RDY, SYNC)
• BIOS: A common BIOS provides the kernel, monitor, and BASIC interpreter across all systems

Systems

Project	Description
6502-ACE	All-in-one Computer Experience — A single board computer (YOU ARE HERE)
6502-COB	Computer On a Backplane — Modular desktop computer with expandable card slots
6502-DEV	Development Environment Vehicle — Emulation-based dev system
6502-KIM	Keypad Input Monitor - KIM-1 inspired minimal computer
6502-VCS	Video Computer System — Cartridge-based retro gaming console

Software

Project	Description
6502-BIOS	The shared BIOS (kernel, monitor, BASIC) for all AC6502 computers
6502-EMULATOR	Emulator for the whole family — desktop app, browser build, and a command line for scripted runs
6502-PRG	Template project for writing assembly language programs
6502-CRT	Template project for writing assembly language cartridges
6502-ASM	Assembly language example programs and demos
6502-BAS	BASIC program listings
6502-WOZMON	Wozmon as a standalone ROM
6502-NOP	An all-NOP ROM, for probing a board during bring-up
6502-DOCS	The documentation site — the guide, the printable reference cards, branding and label artwork
cffs	Builds CompactFlash disk images for the BIOS filesystem
bastok	Tokenizes BASIC listings into .prg images, and back
bin2woz	Converts a binary into a Wozmon serial upload

Hardware

This repository contains KiCad 7.0+ PCB designs for the ACE board.

ACE Board

Hardware/ACE Board/

The single integrated board hosting the W65C02S CPU and all peripherals. Provides:

• CPU: W65C02S running at 1 MHz
• RAM: 32KB SRAM (62256) + Optional 512K banked SRAM (AS6C4008)
• ROM: 32KB EEPROM (28C256)
• Video: Pico9918 (VGA 640×480)
• Audio: ARMSID SID chip emulator (3-voice synthesis, RCA output)
• Storage: Storage adapter socket
• Serial: 65C51 ACIA with MAX238 level shifter (RS-232 via DB9, 50–19200 baud). Male DB-9 wired as DTE, like a PC, so reaching a laptop needs a null-modem cable. RTS, DTR and DSR always reach the cable; the CTS EN and DCD EN jumpers (J2 and J4 on Rev 1.0, J1 and J3 on Rev 1.1) pick ground or the cable for those two inputs — both default to ground
• GPIO: 65C22 VIA (20 GPIO pins, 2× 16-bit timers, shift register)
• RTC: DS1511Y real-time clock with battery-backed NVRAM
• Keyboard Controller: ATmega1284P running AB Controller firmware
• Input: PS/2 keyboard connector and 8×8 keyboard matrix header
• Joystick: Two Atari 2600-compatible joystick ports (JOYSTICK A on VIA PORT A and JOYSTICK B on VIA PORT B — J6 and J8 on Rev 1.0, J5 and J7 on Rev 1.1), read as JOY(2) and JOY(1) respectively
• Clock: 16 MHz DIP-14 full can oscillator (X1); drives the ATmega1284 at 16 MHz and, through the 74HC163 divider (U5), the 65C02, VIA, ACIA and SID at 1 MHz. Rev 1.0 has a PHI2 SELECT jumper (J1) that offers 2 MHz; keep it on 1 MHz (pins 1 and 2), because at 2 MHz the SID, whose clock is always 1 MHz, answers only every other CPU cycle

The serial handshake jumpers. CTS EN and DCD EN (J2 and J4 on Rev 1.0, J1 and J3 on Rev 1.1) both default to ground, and that is how the boards were built. Ground means the line is permanently asserted, so the ACIA can always send and always receive. Moved to the cable, they do real work — measured on a real R6551 in 2026: CTS high stops the transmitter dead and DCD high stops the receiver, losing the byte that arrives. A board jumpered to the cable and plugged into something that does not assert those lines shows no banner and no echo at all, and looks broken when it is not.

• Reset: Manual reset button (SW17, just above Esc) connected to the ATmega1284, which also provides power-on reset to the 65C02
• Power: 5V DC via barrel jack

Revision History

Rev 1.1

• Fixes the gating of the LOADL and LOADH latch-enable signals for the 74HC573 latches (U21, U22) that drive the AS6C4008 banked SRAM. In Rev 1.0 the final two decode gates (U13C/U13D) were NANDs, which left the latches pulsing while idle and allowed spurious loads on reads, so the latches never reliably held a bank value.
• The fix replaces the final NAND stage with a NOR function: LOADL = NOR(SEL_L, WB) and LOADH = NOR(SEH_L, WB), holding each latch enable low out of window and only pulsing on an in-window write. This makes banked RAM work correctly with no firmware change.
• Implemented with one 74HC02 quad NOR beside the 74HC00 U12. Rev 1.0's second 74HC00 in this path is gone, and its designator, U13, now belongs to the 74HC02. Every gate of both chips is in use — the same eight gates as the ACE RAM Patch Rev 1.1: U12A makes /(A9·A8); U13C NORs it with U17's /(A0–A7) to select the bank register; U13D makes IO1 from IO1B and U12D makes B18 from IO2B; U12B and U12C combine the select with IO1 and with B18; and U13A and U13B NOR those with WB to make LOADL and LOADH.
• Fixes the bank register's address decode. U12B combined /(A9·A8) (U12A) and /(A0–A7) (U17) with a NAND, which ORs the two conditions, so each latch also loaded on every write to $8300–$83FE and $80FF, $81FF, $82FF (and the same in the $8400 window). U13C now combines them with a NOR, so each latch loads only on a write to $83FF or $87FF.
• Runs at 1 MHz only. The PHI2 SELECT jumper (Rev 1.0's J1) is removed, and U5's 1 MHz output (Q3) drives PHI2 for the 65C02, VIA, ACIA and SID.
• Adds D1 (BAT85) between the video card's /INT (U3 pin 16) and IRQB, cathode toward U3. The Pico9918 drives /INT high as well as low, and without the diode it held IRQB high against every other interrupt source.
• Adds R5, a 10kΩ pull-up on RESB. The AB Controller firmware now only ever pulls RESB low, so the DS1511Y and cards on CART and BUS can reset the machine too.
• Tests/check-schematics.mjs checks the address decoding of Rev 1.1, and of Rev 1.0 with the ACE RAM Patch Rev 1.1 fitted, in every bus state. See Checking the schematics.
• Some pull-up resistors changed from 1kΩ to 10kΩ: R1–R4 and R26 (Rev 1.0's R25) are now 10kΩ.
• Added C20 (10µF electrolytic) at the power input for bulk decoupling capacitance.
• Re-annotated. Removing J1 and U13, and adding D1 and R5, renumbered the parts after them: in Rev 1.0's terms, the connectors J2–J22 are now J1–J21, the diodes D1–D3 are D2–D4, the resistors R5–R34 are R6–R35, and the capacitors C20–C30 are C21–C31, with the new bulk capacitor at C20. The 74HC02 is U13.

Rev 1.0

• Initial release.

ACE CF Adapter

Hardware/ACE CF Adapter/

A CompactFlash adapter board that connects to the Storage header on the ACE Board. Provides:

• Interface: 8-bit IDE (True IDE) mode
• Storage: CompactFlash socket. The BIOS filesystem divides the card into 256 disk banks of 1 MB each, so 256 MB is the usable capacity regardless of the card fitted

ACE RAM Patch

Hardware/ACE RAM Patch/

A patch board for Rev 1.0 of the ACE Board that corrects the extended RAM (banked SRAM) decoding, with the same logic as Rev 1.1. U12 and U13 come off the ACE, chips and sockets, and the patch is soldered underneath in their place. Provides:

• Fix: LOADL and LOADH go high only on a write to the bank register, $83FF or $87FF, while PHI2 is high. Rev 1.0 pulsed both latches whenever the bus was idle, and the first patch (Rev 1.0) fixed that but still loaded a latch on any write to $8300–$83FE and $80FF–$82FF (and the same in the $8400 window)
• Interface: two DIP-14 footprints of pin headers, J1 into U12's holes and J2 into U13's, soldered on both boards. The patch mounts front side up under the ACE, so its layout is not mirrored; U13's pin 1 is 23.00 mm from U12's pin 1 along the row
• Layout: U1, J1, J2 and U2 in one row, 92.6 × 13.1 mm. J1 and J2 are on the front, facing the ACE; U1 (74HC00) and U2 (74HC02) are on the back, hanging below, so trim their leads flush on the front. The patch hangs about 8.5 mm below the ACE: the header, the board, and the chips
• Rev 1.1: replaces the Rev 1.0 patch, which plugged into U13 alone

Firmware

This repository contains PlatformIO-based firmware for the ACE board.

AB Controller

Firmware/AB Controller/

Firmware for the ATmega1284P keyboard controller on the ACE board. Provides:

• Dual keyboard input: PS/2 and 8×8 matrix keyboard simultaneously
• PS/2 scancode to ASCII conversion
• Matrix keyboard scanning with hardware debouncing
• Modifier key support: Shift (symbols/punctuation) and Ctrl (control codes)
• Buffered output via 65C22 VIA with CA1/CB1 data-ready strobes
• Independent enable/disable for PS/2 and matrix inputs, releasing PORT A / PORT B so the 6502 can read the joysticks that share them
• 6502 reset control: drives RESB on PC7, holding the CPU in reset for ~250 ms at power-on, and debounces the reset button on PC0
• Optional jiffy clock: pulses NMIB from the DS1511Y SQW input; compiled out unless ENABLE_SQW is defined

See Firmware/AB Controller/README.md for setup and usage instructions.

CAD

CAD/

3D-printable enclosure bases and laser-cut top panels for the ACE system.

Production

Production/

JLCPCB-ready Gerber files and BOM/CPL for PCB fabrication and assembly.

Schematics

Schematics/

PDF schematics for the ACE board.

Checking the schematics

Tests/check-schematics.mjs

The banked RAM's latch enables were wrong in Rev 1.0, and wrong again in a different way in the first RAM Patch, and both times the gates looked right on paper. This script checks the logic instead of reading it. It asks KiCad for each board's netlist, builds the glue logic from the gates it finds there, and drives every address, as a read and as a write, with PHI2 high and low and with a cartridge in and out. That is 524,288 bus states per board. For each one it compares every chip select, read and write strobe, and bank latch enable against the memory map, and checks that exactly one chip drives the data bus on a read and exactly one takes a write. A net that nothing drives counts as a failure, so a missing wire fails too.

It checks two boards: Rev 1.1, and Rev 1.0 with the ACE RAM Patch Rev 1.1 fitted. The patch's headers name the sockets they plug into (74HC00 (U12)), and the script pulls those chips and joins each header pin to its socket's net. For Rev 1.1 it also checks that the CPU, VIA, ACIA and SID all run from U5's 1 MHz output, that the video card's /INT reaches IRQB only through a diode, and that RESB has a pull-up.

Run it after any change to either schematic:

node Tests/check-schematics.mjs

It needs Node.js and KiCad's kicad-cli, which it finds on the PATH, at the macOS default location, or through a KICAD_CLI environment variable. It takes about 15 seconds, prints ok or FAIL for each check with example bus states for any failure, and exits non-zero on a failure.

Libraries

Libraries/

Shared KiCad symbol and footprint libraries used across all AC6502 hardware projects.

Bill of Materials

ACE Board

Rev 1.1's designators. Rev 1.0's are in Production/ACE Board/Rev 1.0/bom.csv.

Reference	Qty	Value	Description	DigiKey	Mouser	Other
BT1	1	CR2032	Battery Holder	BAT-HLD-001-THM-ND	712-BAT-HLD-001-THM
C1, C9–C19, C21–C31	23	100nF	Disc Capacitor	478-5732-ND		AMAZON
C2, C3, C5, C6, C8	5	1µF	Disc Capacitor	478-7667-ND		AMAZON
C4, C7	2	2.2nF	Disc Capacitor	478-SR151C222KAATR1CT-ND		AMAZON
C20	1	10uF	Electrolytic Capacitor 16v	P966-ND		AMAZON
D2	1	LED	3.0mm Power LED	732-5008-ND		AMAZON
D1, D3, D4	3	BAT85	Schottky Diode	BAT85SCT-ND	78-BAT85S	AMAZON
J1	1	CTS EN	Pin Header 1×3 2.54mm			AMAZON
J2	1	RESET SW	Pin Header 1×2 2.54mm			AMAZON
J3	1	DCD EN	Pin Header 1×3 2.54mm			AMAZON
J4	1	VDD	Pin Header 1×2 2.54mm			AMAZON
J5	1	JOYSTICK A	DB-9 Male	609-1481-ND	649-D09P33E4GX00LF
J6	1	PADDLES	Pin Header 1×4 2.54mm			AMAZON
J7	1	JOYSTICK B	DB-9 Male	609-1481-ND	649-D09P33E4GX00LF
J8	1	PORT B	Box Header 2×6 2.54mm	2057-BHR-12-VUA-ND		AMAZON
J9	1	PORT A	Box Header 2×6 2.54mm	2057-BHR-12-VUA-ND		AMAZON
J10	1	AUDIO L	RCA Jack	PJRAN1X1U02X-ND	502-PJRAN1X1U02X
J11	1	DB9 MALE (DTE)	DB-9 Male	609-1481-ND	649-D09P33E4GX00LF
J12	1	PS/2	6-pin Mini-DIN		806-KMDGX-6S-BS	AMAZON
J13	1	KEYBOARD	Pin Header 1×16 2.00mm			AMAZON
J14	1	AUDIO R	RCA Jack	PJRAN1X1U03X-ND	502-PJRAN1X1U03X
J15	1	AUDIO	Pin Header 1×2 2.54mm			AMAZON
J16	1	5V DC	DC Barrel Jack	2073-DCJ200-10-A-K1-K-ND	640-DCJ200-10-A-K1-K
J17	1	CART	Card Edge 2×20 2.54mm	A31723-ND	571-5-5530843-4
J18	1	BUS	Box Header 2×20 2.54mm			AMAZON
J19	1	VCC	Pin Header 1×2 2.54mm			AMAZON
J20	1	POWER LED	Pin Header 1×2 2.54mm			AMAZON
J21	1	STORAGE	Pin Socket 2×10 2.54mm Horiz	S5563-ND
R1–R5, R26	6	10kΩ	1/8W Resistor	RNF18FTD10K0CT-ND		AMAZON
R6–R24, R27–R35	28	1kΩ	1/8W Resistor	RNF18FTD1K00CT-ND		AMAZON
R25	1	330Ω	1/8W Resistor			AMAZON
SW1–SW13, SW15, SW18–SW29, SW31, SW33–SW41, SW43, SW44, SW46–SW49, SW51–SW58, SW61, SW64–SW66	54	Various	Cherry MX Switch 1.00u	CH196-ND		AMAZON
SW59, SW60, SW63, SW67, SW68	5	CTRL / ALT / FN	Cherry MX Switch 1.25u	CH196-ND		AMAZON
SW16, SW30	2	TAB / Backslash	Cherry MX Switch 1.50u	CH196-ND		AMAZON
SW32	1	CAPS LOCK	Cherry MX Switch 1.75u	CH196-ND		AMAZON
SW14	1	BACKSPACE	Cherry MX Switch 2.00u	CH196-ND		AMAZON
SW42, SW45, SW50	3	SHIFT / ENTER	Cherry MX Switch 2.25u	CH196-ND		AMAZON
SW62	1	SPACE	Cherry MX Switch 6.25u	CH196-ND		AMAZON
SW17	1	RESET	Tact Push Button 6mm			AMAZON
SW69	1	POWER	SPDT Switch	EG4326-ND	612-400MSP1R6BLKM6QE
SW70	1	IO ENABLE	8× DIP Switch SPST			AMAZON
U1	1	W65C02S	65C02 CPU		955-W65C02S6TPG-14
U2	1	W65C22	65C22 VIA		955-W65C22N6TPG-14
U3	1	Pico9918A	VDP (VGA)			TINDIE
U4	1	65C51	ACIA			JAMECO
U5	1	74HC163	4-bit Counter	296-8246-5-ND	595-SN74HC163N
U6	1	ATmega1284-P	Keyboard Controller MCU	ATMEGA1284-PU-ND	556-ATMEGA1284-PU
U7	1	AS6C62256	32KB SRAM	1450-1033-ND	913-AS6C62256-55PCN
U8	1	AT28C256	32KB EEPROM	AT28C256-15PU-ND	556-AT28C25615PU
U9	1	6581	SID Chip			LINK
U10	1	MAX238xNG+	RS-232 Transceiver	MAX238CNG+-ND	700-MAX238CNG
U11, U12, U14, U16	4	74HC00	Quad NAND	296-1563-5-ND	595-SN74HC00N
U13	1	74HC02	Quad NOR	296-1565-5-ND	595-SN74HC02N
U15	1	AS6C4008	512KB SRAM	1450-1027-ND	913-AS6C4008-55PCN
U17	1	74HC30	8-input NAND	296-9196-5-ND	595-CD74HC30E
U18	1	DS1511Y	RTC + NVRAM	DS1511Y+-ND	700-DS1511Y
U19, U20	2	74HC138	3-to-8 Decoder	296-1575-5-ND	595-SN74HC138N
U21, U22	2	74HC573	Octal Latch	296-12815-5-ND	595-CD74HC573EE4
X1	1	16MHz	DIP-14 Oscillator	X947-ND	815-ACO-16-EK
Y1	1	1.8432MHz	Crystal	3155-1.8432M20P2/49U-ND	815-AB-1.8432-B2

ACE CF Adapter

Reference	Qty	Value	Description	DigiKey	Mouser	Other
D1	1	ACT LED	3.0mm LED	732-5008-ND		AMAZON
J1	1	STORAGE	Pin Header 2×10 2.54mm Horiz			AMAZON
J2	1	Compact Flash	CF Socket	4827-101D-TAAB-R01-ND
R1–R4	4	1kΩ	1/8W Resistor	RNF18FTD1K00CT-ND		AMAZON
R5	1	330Ω	1/8W Resistor			AMAZON

ACE RAM Patch

Reference	Qty	Value	Description	DigiKey	Mouser	Other
J1	1	74HC00 (U12)	Pin Header 1×7 2.54mm ×2, soldered between the boards
J2	1	74HC00 (U13)	Pin Header 1×7 2.54mm ×2, soldered between the boards
U1	1	74HC00	Quad NAND	296-1563-5-ND	595-SN74HC00N
U2	1	74HC02	Quad NOR	296-1565-5-ND	595-SN74HC02N

License

Hardware designs are released under the CERN Open Hardware Licence Version 2 – Permissive.
Firmware is released under the MIT License.