zephyr-cp: add the Silicon Labs SiWx917-DK2605A

ports/zephyr-cp/Makefile

@@ -42,6 +42,9 @@ $(BUILD)/firmware.exe: $(BUILD)/zephyr-cp/zephyr/zephyr.elf
 $(BUILD)/firmware.uf2: $(BUILD)/zephyr-cp/zephyr/zephyr.elf
 	cp $(BUILD)/zephyr-cp/zephyr/zephyr.uf2 $@
 
+$(BUILD)/firmware.rps: $(BUILD)/zephyr-cp/zephyr/zephyr.elf
+	cp $(BUILD)/zephyr-cp/zephyr/zephyr.rps $@
+
 flash: $(BUILD)/zephyr-cp/zephyr/zephyr.elf
 	west flash -d $(BUILD)
 

ports/zephyr-cp/boards/board_aliases.cmake

@@ -55,3 +55,4 @@ cp_board_alias(raspberrypi_rpi_pico_w_zephyr rpi_pico/rp2040/w)
 cp_board_alias(raspberrypi_rpi_pico2_zephyr rpi_pico2/rp2350a/m33)
 cp_board_alias(raspberrypi_rpi_pico2_w_zephyr rpi_pico2/rp2350a/m33/w)
 cp_board_alias(st_nucleo_n657x0_q nucleo_n657x0_q/stm32n657xx)
+cp_board_alias(silabs_siwx917_dk2605a siwx917_dk2605a)

ports/zephyr-cp/boards/silabs/siwx917_dk2605a/autogen_board_info.toml

@@ -0,0 +1,129 @@
+# This file is autogenerated when a board is built. Do not edit. Do commit it to git. Other scripts use its info.
+name = "Silicon Labs SiWx917 Wi-Fi 6 and Bluetooth LE SoC Dev Kit (BRD2605A)"
+
+[modules]
+__future__ = true
+_bleio = true # Zephyr board has _bleio
+_eve = false
+_pew = false
+_pixelmap = false
+_stage = false
+adafruit_bus_device = true
+adafruit_pixelbuf = false
+aesio = true
+alarm = false
+analogbufio = false
+analogio = false
+atexit = false
+audiobusio = false
+audiocore = false
+audiodelays = false
+audiofilewriter = false
+audiofilters = false
+audiofreeverb = false
+audioi2sin = false
+audioio = false
+audiomixer = false
+audiomp3 = false
+audiopwmio = false
+audiospeed = false
+aurora_epaper = false
+bitbangio = false
+bitmapfilter = true # Zephyr board has busio
+bitmaptools = true # Zephyr board has busio
+bitops = false
+board = false
+busdisplay = true # Zephyr board has busio
+busio = true # Zephyr board has busio
+camera = false
+canio = false
+codeop = false
+countio = false
+digitalio = true
+displayio = true # Zephyr board has busio
+dotclockframebuffer = false
+dualbank = false
+epaperdisplay = true # Zephyr board has busio
+floppyio = false
+fontio = true # Zephyr board has busio
+fourwire = true # Zephyr board has busio
+framebufferio = true # Zephyr board has busio
+frequencyio = false
+getpass = true
+gifio = true # Zephyr board has busio
+gnss = false
+hashlib = true # Zephyr networking enabled
+hostnetwork = false
+i2cdisplaybus = true # Zephyr board has busio
+i2cioexpander = false
+i2ctarget = false
+imagecapture = false
+ipaddress = true # Zephyr networking enabled
+is31fl3741 = false
+jpegio = true # Zephyr board has busio
+keypad = false
+keypad_demux = false
+locale = false
+lvfontio = true # Zephyr board has busio
+math = true
+max3421e = false
+mcp4822 = false
+mdns = false
+memorymap = false
+memorymonitor = false
+microcontroller = true
+mipidsi = false
+msgpack = true
+neopixel_write = false
+nvm = false
+onewireio = false
+os = true
+paralleldisplaybus = false
+ps2io = false
+pulseio = false
+pwmio = false
+qrio = false
+qspibus = false
+rainbowio = true
+random = true
+rclcpy = false
+rgbmatrix = false
+rotaryio = true # Zephyr board has rotaryio
+rtc = false
+sdcardio = true # Zephyr board has busio
+sdioio = false
+sharpdisplay = true # Zephyr board has busio
+socketpool = true # Zephyr networking enabled
+spitarget = false
+ssl = true # Zephyr networking enabled
+storage = true
+struct = true
+supervisor = true
+synthio = false
+terminalio = true # Zephyr board has busio
+tilepalettemapper = true # Zephyr board has busio
+time = true
+touchio = false
+traceback = true
+uheap = false
+usb = false
+usb_audio = false
+usb_cdc = false
+usb_hid = false
+usb_host = false
+usb_midi = false
+usb_video = false
+ustack = false
+vectorio = true # Zephyr board has busio
+warnings = true
+watchdog = false
+wifi = true # Zephyr board has wifi
+zephyr_display = false
+zephyr_kernel = false
+zlib = true
+# extmod modules shared with MicroPython
+asyncio = true
+binascii = true
+json = true
+re = true
+select = true

ports/zephyr-cp/boards/silabs/siwx917_dk2605a/circuitpython.toml

@@ -0,0 +1 @@
+CIRCUITPY_BUILD_EXTENSIONS = ["rps"]

ports/zephyr-cp/boards/siwx917_dk2605a.conf

@@ -0,0 +1,93 @@
+# The upstream board defconfig does not enable GPIO, so no gpio device structs
+# are instantiated and the generated board.c fails to link.
+CONFIG_GPIO=y
+
+# getaddrinfo() calls k_calloc(), which is compiled out when the kernel heap is
+# zero-sized. prj.conf also draws thread stacks from this heap.
+CONFIG_HEAP_MEM_POOL_SIZE=16384
+
+CONFIG_NETWORKING=y
+CONFIG_NET_IPV4=y
+CONFIG_NET_DHCPV4=y
+CONFIG_NET_SOCKETS=y
+
+# Not implied by the options above, and the siwx91x driver defaults to the
+# native stack. Without it association and DHCP still work, since DHCP is UDP,
+# while every SOCK_STREAM socket fails.
+CONFIG_NET_TCP=y
+
+# Every Zephyr socket also takes a zvfs file descriptor, which defaults to 0.
+CONFIG_ZVFS_OPEN_MAX=8
+
+# Poll slots for the socket-service thread, a separate budget from OPEN_MAX.
+# The thread polls one entry beyond the number of registered services, so this
+# must be strictly greater than that count. DNS_RESOLVER registers one service
+# and MDNS_RESPONDER two, so the Zephyr default of 3 is one short and the
+# service thread fails at boot, leaving every socket it owns unread.
+CONFIG_ZVFS_POLL_MAX=6
+
+# dns_resolve_reconfigure() is additive by default: it fills free slots and
+# stops when there are none, then still returns 0. With one server slot held by
+# DHCP, assigning to radio.dns would install nothing and report success. This
+# makes reconfigure rebuild the list instead, which is the replace semantics
+# the binding implies by exposing dns as a settable Sequence[str].
+CONFIG_DNS_RECONFIGURE_CLEANUP=y
+
+# Incoming connections are bounded by the net_conn array, not the TCP context
+# slab. At the default of 8 the web workflow refuses connections during a burst
+# because teardown cannot recycle slots fast enough, since each closed
+# connection holds its slot for TIME_WAIT. 12 leaves enough headroom, and the
+# context slab is raised alongside it so the slab is not the tighter bound.
+CONFIG_NET_MAX_CONTEXTS=12
+CONFIG_NET_MAX_CONN=12
+
+# Zephyr's console (printk, boot banner, driver logs) goes to SEGGER RTT over
+# the existing SWD connection rather than sharing the UART with the REPL, where
+# net event printks interleave with and corrupt the REPL stream. CircuitPython's
+# REPL is unaffected: supervisor/serial.c takes its device from
+# DT_CHOSEN(zephyr_console) and drives it directly.
+CONFIG_USE_SEGGER_RTT=y
+CONFIG_RTT_CONSOLE=y
+CONFIG_UART_CONSOLE=n
+
+CONFIG_WIFI=y
+CONFIG_NET_L2_WIFI_MGMT=y
+CONFIG_NET_MGMT_EVENT=y
+CONFIG_NET_MGMT_EVENT_INFO=y
+
+# Answers <hostname>.local and advertises services registered through
+# mdns.Server.advertise_service(). Zephyr's responder is push-only, so
+# mdns.Server.find() has nothing to search with yet.
+CONFIG_MDNS_RESPONDER=y
+CONFIG_DNS_SD=y
+CONFIG_MDNS_RESPONDER_DNS_SD=y
+
+CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
+CONFIG_MBEDTLS_CIPHERSUITE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256=y
+CONFIG_MBEDTLS_ENTROPY_C=y
+CONFIG_MBEDTLS_CTR_DRBG_C=y
+
+# Long writes need at least one prepare slot. Zephyr's unconditional default of
+# 0 rejects any write that does not fit a single ATT_WRITE_REQ, and only an
+# explicit assignment here overrides it.
+CONFIG_BT_ATT_PREPARE_COUNT=2
+
+# Zephyr's default preferred supervision timeout is 420ms, which the peripheral
+# pushes onto the central shortly into every connection. That is thin on a
+# single-antenna part whose network processor shares the radio with Wi-Fi.
+# 400 = 4.0s, Apple's accessory guideline value.
+CONFIG_BT_PERIPHERAL_PREF_MIN_INT=24
+CONFIG_BT_PERIPHERAL_PREF_MAX_INT=40
+CONFIG_BT_PERIPHERAL_PREF_LATENCY=0
+CONFIG_BT_PERIPHERAL_PREF_TIMEOUT=400
+
+# The controller reports 15 ACL TX buffers while the host defaults to 3, which
+# it warns about at boot. Match the host to the controller.
+CONFIG_BT_BUF_ACL_TX_COUNT=15
+
+# DHCP hands us a resolver, but the resolver subsystem has to be present for
+# socketpool.getaddrinfo() and radio.ipv4_dns to work.
+CONFIG_DNS_RESOLVER=y
+
+# DMA for the GSPI controller, which serves the breakout pads.
+CONFIG_DMA=y

ports/zephyr-cp/boards/siwx917_dk2605a.overlay

@@ -0,0 +1,69 @@
+// Replaces the port's app.overlay, which does `&zephyr_udc0 { ... }` to add a
+// CDC-ACM console. The SiWG917 has no USB device controller, so the console
+// falls back to the Zephyr console on &ulpuart, reaching the host over the
+// on-board J-Link VCOM.
+
+// CIRCUITPY filesystem.
+//
+// supervisor/flash.c needs a partition labeled `circuitpy_partition`, and the
+// whole 8 MB is already partitioned by siwg917m111mgtba.dtsi with no
+// unallocated space to claim. The upper region is owned by the network
+// processor, which refuses M4 writes there, so CIRCUITPY is carved out of the
+// M4's own code_partition, shrunk from 2008K to 1M. Overflowing that fails at
+// link time rather than corrupting the filesystem.
+&flash0 {
+	partitions {
+		code_partition: partition@202000 {
+			compatible = "zephyr,mapped-partition";
+			label = "code_partition";
+			reg = <0x00202000 0x00100000>;
+		};
+
+		circuitpy_partition: partition@302000 {
+			compatible = "zephyr,mapped-partition";
+			label = "circuitpy";
+			reg = <0x00302000 0x000f6000>;
+		};
+	};
+};
+
+// GSPI on the breakout pads. The board .dts leaves spi0 disabled and wires
+// nothing, so the pin assignment here is taken from the mapping Silicon Labs
+// ships for this board in
+// zephyr/tests/drivers/spi/spi_loopback/boards/siwx917_dk2605a.overlay:
+// CLK on pad 3, MOSI on pad 5, MISO on pad 7, CS on gpiob 12.
+//
+// spi0 is the SoC's only SPI controller node and is compatible "silabs,gspi".
+// The on-board IMU is on a separate ULP SPI bus that has no controller node in
+// devicetree, so it is not reachable through this one.
+&pinctrl0 {
+	spi0_default: spi0_default {
+		out {
+			pinmux = <GSPI_CLK_HP25>, <GSPI_MOSI_HP27>;
+		};
+
+		in {
+			pinmux = <GSPI_MISO_HP26>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+	cs-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+
+	dmas = <&gpdma 0 11>, <&gpdma 1 10>;
+	dma-names = "tx", "rx";
+};
+
+&gpdma {
+	status = "okay";
+};
+
+// 8 MB of PSRAM on the QSPI2 path. Present in ram_bounds; the Python heap does
+// not use it yet.
+&psram {
+	status = "okay";
+};