zephyr-cp: add pwmio for nordic boards

[dhalbert]

Claude wrote most of the code, with @dhalbert steering, reviewing and testing.

• Add pwmio for the zephyr-cp port on Nordic. IOBroker already had some support for PWM due to neopixel_write.
• iobroker allocates PWM channels in period groups. On nRF a group is one instance, whose four outputs share a period.
  • iobroker_pwm_channel_allocate(pin, frequency, exclusive, ...) returns a device and channel. It doesn't actually set the frequency. It uses the frequency only to choose a group, either a running group requested at the same frequency, or else a free instance.
  • Joining or leaving a running group configures only that output's PSEL, so the group's other outputs are not disturbed.
  • An exclusive request gets a group of its own. A variable_frequency=True PWMOut sets exclusive, so it can change its period without affecting other channels.
  • iobroker_pwm_channel_release() returns the channel. The group's last channel releases the instance.
• common-hal/pwmio turns the frequency into a period itself, with pwm_get_cycles_per_sec(). The period is truncated, as in ports/nordic, so the actual frequency is the same or slightly higher.
• neopixel_write now allocates an exclusive channel, which on nRF is a whole instance. There is no separate whole-instance allocator.

Not in this PR

• Frequency range checking. pwm_nrfx doesn't reject every period it can't produce: it accepts 1–3 Hz, and about 5.3–8 MHz. This will be fixed separately, by a validator or by patching the drivers.

Future pwmio implementations

• The group bookkeeping lives in the nRF implementation. SoCs group channels very differently: for example, on nRF any pin can join any instance, while an RP2 slice is fixed by the pin. So if there's some PWM group code to share, it can wait for another implementation.
• common-hal/pwmio uses only Zephyr's PWM API. Another SoC needs just an iobroker implementation; an RP2 slice or an STM32 timer would be a group.

Tests

• New pwm_emul module for tests: an emulated PWM controller, adafruit,pwm-emul, that traces each pin's period and pulse as Perfetto counter tracks. native_sim gets one channel per pin and two period groups that any channel can join. This models only the pwmio rules every port shares, not any SoC's layout.
• New tests/test_pwmio.py: frequency and duty conversion, the reported frequency, frequency changes, invalid frequencies, pin claims, group sharing and exhaustion, and variable-frequency groups.

Testing

Board	Checks
Feather nRF52840 Express	Logic analyzer: three channels sharing an instance at 1 kHz (25/50/75 %) and one at 2 kHz, exact to 20 ns. A channel joining and leaving 200 times, and OUT0 leaving and rejoining 200 times, did not disturb running channels. REPL: sharing, running out of instances, variable frequency, invalid frequencies, release. neopixel_write on an RGBW ring and the status NeoPixel, on the PWM path and on the bit-bang fallback with every instance held by pwmio.
nRF54LM20 DK	Same logic analyzer checks, at 3.3 V. P2 and P0 pins raise ValueError.
nRF54L15 DK	REPL checks. P2 and P0 pins raise ValueError.
native_sim	test_pwmio.py on native_sim, native_sim_asan and native_sim_lfs.

[tannewt]

Thanks for this! I like the perfetto output used in tests. I added a couple comments about the IOBroker API.

[dhalbert]

Ready for re-review. Whole PWM allocator removed, as described above. Did not attempt to ameliorate lousy arg validation in SOC-specific pwm_set_cycles() implementations, as we discussed.

[tannewt]

Looks good! Thank you!