fix: update arena trim for current llama-context APIs - #6
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Fix two compile regressions in the scratch-arena trim port introduced by 433ae2c. Current upstream no longer has the historical src_ctx member used by the old ROCmFPX safety gate, so remove that stale check. The remaining target-context gate through cparams.ctx_type / cparams.ctx_other still prevents applying the optimization to the MTP/secondary context. Also cast llm_graph_result::get_max_nodes() to size_t before std::max(). Current upstream returns int64_t there, while ggml_backend_sched_new() expects a size_t graph size; GCC correctly rejects template deduction across the two different integer types. These are compile-only adaptations. They do not change when arena trimming is enabled, its 32 MiB threshold, scheduler replacement behavior, or the historical Qwen35/single-GPU/max2/ubatch512 safety envelope.
bryanwieg
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Rebase the indexed recurrent-state optimization onto the current rx9070-port after the arena-trim compile fixes from PR #6. The normal recurrent graph gathers the selected persistent GDN state row into a packed scratch tensor before every fused gated-delta-net invocation. With GGML_ROCM_GDN_INDEXED_STATE=single-v1, the qualified RX 9070 path instead passes the persistent F32 state bank plus a dynamic I32 row selector directly to GGML_OP_GATED_DELTA_NET_INDEXED. The HIP kernel reads the selected bank row on device, avoiding the GET_ROWS state gather while preserving the ordinary GDN output and snapshot writeback path. The optimization remains default-off and deliberately narrow: - HIP RDNA4 backend - one sequence and one recurrent-state selection - Qwen35 geometry S_v=128, H_v=48, H_k=16 - K=3 (n_rs_seq=2), 1..3 tokens - F32 contiguous ordinary device state bank - fused autoregressive/chunked GDN enabled A backend capability query prevents the model graph from assuming that an arbitrary GPU buffer supports this operation. An explicit state-dependency input preserves zero-initialization ordering. CPU execution is implemented for correctness/fallback; non-qualified shapes retain the existing graph. Historical RX 9070 / Windows ROCm evidence measured 24-46% reduction in the target GDN state-access component and about +3.2% mean end-to-end decode in one ABBA run (OFF 53.863/51.978 vs ON 54.500/54.692 t/s), with matching outputs and speculative token counts. The original investigation also noted run-to-run drift, so this port does not claim a universal TPS gain until it is re-benchmarked on current upstream. This port excludes the later direct-write fusion WIP, graph-capture diagnostics, snapshot-copy experiments, and all ROCmFPX quantization code. Source: 21edd46f773765db02bbae1d480bc68d1ed97115
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The manual PR build exposed two compile errors inherited from the merged arena-trim port:
src_ctxreference from the historical implementationstd::max(size_t, int64_t)type mismatch around graph-node sizingThis PR only adapts those checks/types to current upstream APIs; it does not change the optimization policy or thresholds.
Both the CPU and HIP jobs for PR #4 stopped on these same errors before reaching the indexed-GDN changes.