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RISC-V regression builds ran only at -O0, leaving a timer callback counter that spins forever at -O2. The trace regression was excluded because it referenced a port-specific interrupt-save variable, and its adjacent pools could start misaligned on RV64. Made the timer counter volatile, gave the trace test aligned pool storage and a portable saved-interrupt value, and enabled it on RISC-V. Added an -O2 QEMU configuration to keep the optimized failure covered. CMake/Ninja/QEMU: RV64 default, optimized and trace suites passed 97/97 each; RV32 passed 96/96 each. Two ISR event tests passed 30 repeats each at -O2. The Linux/GCC 14 trace test passed. The reported timing resonance did not recur. Assisted-by: Codex (gpt-6-sol) <noreply@openai.com>
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RISC-V regression builds ran only at
-O0, which hid a timer callback counter that made the multi-level preemption test hang at-O2. The trace test was excluded because it used a port-specific interrupt-save variable, and its byte pool could start at an unaligned address. These are among the portability concerns in #520.The timer counter is now volatile. The trace test uses aligned pool storage and a portable interrupt-save variable, so it runs on RV32 and RV64. An optimized QEMU configuration keeps the higher-optimization failure in CI.
CMake/Ninja/QEMU passed RV64 default, optimized, and trace suites at 97/97 each, and RV32 at 96/96 each. PR CI passed 1,158/1,158 RISC-V tests; the ThreadX, SMP, and FreeRTOS checks also passed. The two ISR event tests passed 30 repeats each at
-O2; the reported timing resonance did not recur on QEMU. The Linux/GCC 14 trace test passed. Not run on hardware.