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Pull requests: llvm/circt

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Pull requests list

[ImportVerilog][MooreToCore] Adds support for System Verilog real maths functions
#10746 opened Jun 30, 2026 by jpkirs Loading…
[Python] Fix ModuleLike.is_external for ops with no region
#10745 opened Jun 30, 2026 by uenoku Member Loading…
1
[FIRRTL] Add edge attribute to LTL clock intrinsic
#10744 opened Jun 29, 2026 by Clo91eaf Contributor Loading…
1
Adding support for the Verilog Real Math system as non synthesisable constructs
#10743 opened Jun 29, 2026 by jpkirs • Draft
[FIRRTL][Seq] Make register reset semantics explicit
#10742 opened Jun 28, 2026 by Clo91eaf Contributor • Draft
4
[RFC] Add Probe dialect prototype for HW-level probe modeling
#10741 opened Jun 27, 2026 by nanjo712 Contributor Loading…
4
[Arc] Add LowerProcesses pass Arc Involving the `arc` dialect
#10740 opened Jun 26, 2026 by fabianschuiki Contributor Loading…
2
[ExportVerilog] Fix enum case labels for anonymous enumerations
#10739 opened Jun 26, 2026 by ConvolutedDog Loading…
1
[FIRRTL] Add LTLClockedDelayIntrinsicOp in FIRRTL
#10737 opened Jun 26, 2026 by Clo91eaf Contributor • Draft
3
[Synth] Use LinearTimingArcAttr sensitivity in TechMappper
#10735 opened Jun 25, 2026 by okekayode Contributor Loading…
1
[FIRRTL][Dedup] Reuse NLA in addAnnotationContext for singly instantiated module
#10731 opened Jun 24, 2026 by uenoku Member Loading…
8
[TableGen] Make dialect TableGen files self-contained
#10724 opened Jun 24, 2026 by ConvolutedDog Loading…
2
[Moore][Sim] Add %l/%L library binding format specifier
#10716 opened Jun 23, 2026 by VecoMr Member Loading…
6
[MooreToCore] Convert debug value and enum wrappers
#10714 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Fold zero-width unpacked array comparisons
#10713 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Lower real and time value conversions
#10712 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Lower real math and clog2 builtins
#10711 opened Jun 22, 2026 by AmurG Contributor Loading…
4
[MooreToCore] Lower handle and event value conversions
#10710 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Skip bodies for pure virtual non-void methods
#10709 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Lower packed aggregate extraction forms
#10708 opened Jun 22, 2026 by AmurG Contributor Loading…
2
[MooreToCore] Lower aggregate storage and value materialization
#10707 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Lower procedural fork/wait/assert/loop statements
#10706 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[MooreToCore][MapArithToComb] Lower queue and non-HW select boundaries
#10705 opened Jun 22, 2026 by AmurG Contributor Loading…
2
[MooreToCore] Build legal implicit sensitivity for value refs
#10704 opened Jun 22, 2026 by AmurG Contributor Loading…
2
[ImportVerilog][MooreToCore] Legalize format string boundaries
#10703 opened Jun 22, 2026 by AmurG Contributor Loading…
2
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