[ahalekelly]

🤖 Generated with Claude Fable 5.2

Sets bit 0 of register 0x08B5 on every SX1262 board at init and after an AGC reset, instead of only the five boards with SX126X_REGISTER_PATCH. Without it, a strong signal a few MHz off channel can leave the AGC stuck at low gain: RSSI sits near −76 dBm, 0x08BF/0x08C0 read 08/12 instead of 60/6C, and the node is deaf until receive restarts. A RAK4631 companion here went deaf with the same symptoms for up to hours at a time.

Tested at 910.525 MHz, BW 62.5 kHz, SF7, CR 4/5. The blocker was a 30 ms unmodulated carrier of about 1 mW from a second SX1262 board, antennas about 20 cm apart, within ±5 MHz of the channel and −20 to −37 dBm at the victim by its own RSSI. The bit was toggled by register write in alternating blocks on v1.18.0.

SX1262 board	Bit clear: locks / bursts	Bit set: locks / bursts
RAK4631	52/60	0/1,000
Seeed Wio Tracker L1	95/120	0/120
RAK3401 + RAK13302 1 W	39/90	0/120

Lock rate peaks in a level window about 2 dB wide that differs by board and frequency; the bit-clear column is each board's worst level. With this change cherry-picked onto v1.18.0, a Wio Tracker L1 read 05 after boot and after an AGC reset and locked in 0 of 120 bursts, against 54 of 60 with the bit then cleared. Without a carrier, the RAK4631 heard 91.3% of a reference node's packets with the bit clear and 89.6% with it set (±7 points).

SX1268, LLCC68 and STM32WL are unchanged because only SX1262 was measured. Debug firmware and test script: https://github.com/ahalekelly/MeshCore/tree/agc-lock-test/agc-lock-test

[nullrouten0]

#1398