[DiyouS]

Add bypass path for Spatz and Snitch

[Copilot]

🟡 Changes recommended

Unresolved correctness issues can compromise memory transactions, preserve neither cached data nor configuration compatibility, and hide test failures.

5 open issues

• Preserve conventional cache configuration when bypass is disabled · New
• Align bypass AXI addresses to beat boundaries · New
• Avoid data loss when l1d_commit reinitializes the cache · New
• Cached counters remain stale across tile-private banks · New
• Reject oversized configurations before array access and collective setup · New

What changed in this PR

Adds a runtime-controlled L1 data-cache bypass path for Spatz and Snitch, connecting private-range accesses directly to DRAM through the existing refill infrastructure.

Changes:

• Adds bypass control registers, routing metadata, and a dedicated single-beat AXI converter.
• Exposes runtime controls and linker storage, with a directed test registered in both CI configurations.
• Updates monitoring and refill-width defaults, and adds FFT stage synchronization for dual-scalar configurations.

File	Description
software/​tests/​l1-bypass/​main.c	Tests scalar/vector bypass accesses, visibility, and timing.
software/​tests/​CMakeLists.txt	Registers the bypass test.
software/​snRuntime/​src/​l1cache.c	Implements runtime bypass control.
software/​snRuntime/​link/​common.ld.in	Adds the bypass memory region and section.
software/​snRuntime/​include/​l1cache.h	Declares the bypass API and cache-maintenance contract.
software/​snRuntime/​include/​cachepool_peripheral.h	Adds bypass register definitions and shifts crossbar offsets.
software/​kernels/​fp/​fft-32b/​kernel/​fft.c	Fences intermediate FFT stages on dual-scalar configurations.
hardware/​tb/​tb_cachepool.sv	Uses the expanded DRAM AXI user width.
hardware/​tb/​cachepool_monitor.sv	Separates bypass traffic statistics from cache refills.
hardware/​src/​cachepool_tile.sv	Connects bypass controls and metadata to cache controllers.
hardware/​src/​cachepool_reqrsp_to_axi.sv	Adds single-beat AXI conversion with bypass payload handling.
hardware/​src/​cachepool_pkg.sv	Defines bypass parameters, metadata, and widened AXI types.
hardware/​src/​cachepool_group.sv	Forwards bypass control and updates request metadata.
hardware/​src/​cachepool_group_noc_wrapper.sv	Registers and forwards bypass control.
hardware/​src/​cachepool_cluster.sv	Integrates DRAM converters and bypass assertions.
hardware/​cachepool_peripheral/​cachepool_peripheral.sv	Applies bypass configuration on commit.
hardware/​cachepool_peripheral/​cachepool_peripheral_reg.hjson.tmpl	Defines the bypass control register.
hardware/​cachepool_peripheral/​cachepool_peripheral_reg_top.sv	Implements register storage and decoding.
hardware/​cachepool_peripheral/​cachepool_peripheral_reg_pkg.sv	Updates register types, offsets, and permissions.
config/​README.md	Documents the full-line refill-width requirement.
config/​config.mk	Defaults refill width to 512 bits and updates comments.
config/​cachepool_fpu_4g.mk	Corrects the DRAM-selection comment only.
config/​cachepool_fpu_16g.mk	Corrects the DRAM-selection comment only.
config/​cachepool_fpu_16g_tiny.mk	Corrects the DRAM-selection comment only.
config/​cachepool_dual_fpu_4g.mk	Corrects the DRAM-selection comment only.
config/​cachepool_dual_fpu_16g.mk	Corrects the DRAM-selection comment only.
config/​cachepool_dual_4g.mk	Corrects the DRAM-selection comment only.
config/​cachepool_4g.mk	Corrects the DRAM-selection comment only.
Bender.yml	Includes the new AXI converter source.
Bender.lock	Updates the Insitu-Cache dependency revision.
.gitlab-ci.yml	Adds bypass testing to standard and dual-scalar jobs.

_{Review effort: Balanced}