feat(#851): aarch64 full control flow — if/else, loop, return

[avrabe]

Summary

Extends the -b aarch64 backend's void-block-only #538 control flow
(block/br/br_if) with the remaining structured constructs, part of lane
L4 of the v0.51 hub. Closes the last major control-flow gap for the host-native
integer subset (#851).

Lowered (all execution-verified bit-identical vs wasmtime):

• if/else — cbz cond → else/end, unconditional b over the else arm,
  join at end (void (0,0) only).
• loop — backward branch target: a br/br_if to a loop frame resolves a
  negative offset eagerly at the loop header (void (0,0) only).
• return — early epilogue (funnel top → x0/d0, restore SP, ret).

Design

• Kind-tagged control frames. enum Kind { Block, Loop { entry }, If { else_fixup } }.
  Branch resolution dispatches on the target frame's kind — Block/If are
  forward (recorded in pending, patched at End), Loop is backward (resolved
  on emission). This is what lets loop back-edges and forward block exits coexist.
• patch_branch helper centralizes the b/cbnz/cbz re-encode so the new
  cbz can't be mis-patched as a cbnz; it is fallible and range-checks every
  displacement.
• Reachability flag applies WASM's stack-polymorphism rule after
  br/return/unreachable: the value stack is truncated unconditionally
  (fixes the model) but the fall-through height debug_assert is gated on
  reachability.
• block_arity ordinal is now consumed by Loop and If (one entry each),
  keeping the arity-table lookup aligned.
• Range guards (check_imm26/check_imm19): displacements exceeding the A64
  field width LOUD-DECLINE rather than wrap silently.

Honest frontier (loud-decline, never silent)

• Value-producing if/loop (arity ≠ (0,0) — both arms would need the result
  in one register / the value stack live across the back-edge).
• br_table (catch-all).
• Over-range branch displacements.

Gate — RED-first execution differential

scripts/repro/aarch64_ctrlflow_851_differential.py (28 cases), native arm64
(MAP_JIT fork) + unicorn vs wasmtime:

• RED before: all 7 functions declined (If unsupported, loop declined by name).
• GREEN after: 28/28 bit-identical — if/else (both arms), counting + countdown +
  do-while loops (the do-while drives the backward conditional cbnz-to-header
  path), early-return, return-inside-loop. Both branch edges + a trap edge
  exercised; non-vacuity-guarded (every function + both edges must run).

Verification

• Backend unit tests 70/70 (new: void-if cbz skip, if/else both-edge patch, loop
  back-edge negative offset, early-return epilogue).
• scripts/repro/aarch64_matrix.sh PASS (32 ops accepted, 86 native checks).
• Pre-existing aarch64_cf_538 / locals_851 / mem_851 differentials still GREEN.
• frozen_codegen_bytes 10/10 untouched.
• cargo fmt --check + cargo clippy --workspace --all-targets -D warnings clean.

Coordinator note

The new differential needs wiring into .github/workflows/ci.yml alongside
aarch64_cf_538_differential.py / aarch64_mem_851_differential.py at assembly
(this lane does not edit repo config).

🤖 Generated with Claude Code

https://claude.ai/code/session_01YJK5LZZEkV5smCY1jKn18L

[codecov]

Codecov Report

❌ Patch coverage is 93.02326% with 12 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
crates/synth-backend-aarch64/src/selector.rs	93.02%	12 Missing ⚠️

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