IMX708 ccs and link frequency changes - #7605
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…ites Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com>
When the PLL is configured in DUAL_MODE (separate VT and OP trees) and the sensor's FIFOs allow derating and/or overrating, the VT pixel rate might be higher or lower than OP pixel rate. Support such usecases by allowing an optional input for the target VT pixel rate. Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com>
Replace the PLL dividers and multipliers hard coded into the mode and link frequency register lists with a call to the CCS PLL calculator, describing the sensor clock tree limits from its manual. The pre-PLL dividers are pinned to the values those register lists used, so the tree the calculator arrives at is the one the driver has always programmed, which was confirmed against every mode at every link frequency.
Give each mode an array of timings rather than one fixed set, so that a mode can run faster when the link has the bandwidth for it. A mode uses the higest link frequency timings specified. Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Add timings for a 960MHz link frequency, which gives the full resolution mode enough bandwidth to reach 30fps and roughly doubles the rate of the binned modes. Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
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