chore(c0): update to latest STM32CubeC0 v1.4.1

system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h

@@ -4239,10 +4239,8 @@ typedef struct
 #define RCC_CSR1_LSEBYP_Msk              (0x1UL << RCC_CSR1_LSEBYP_Pos)         /*!< 0x00000004 */
 #define RCC_CSR1_LSEBYP                  RCC_CSR1_LSEBYP_Msk
 #define RCC_CSR1_LSEDRV_Pos              (3U)
-#define RCC_CSR1_LSEDRV_Msk              (0x3UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000018 */
+#define RCC_CSR1_LSEDRV_Msk              (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
 #define RCC_CSR1_LSEDRV                  RCC_CSR1_LSEDRV_Msk
-#define RCC_CSR1_LSEDRV_0                (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
-#define RCC_CSR1_LSEDRV_1                (0x2UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000010 */
 #define RCC_CSR1_LSECSSON_Pos            (5U)
 #define RCC_CSR1_LSECSSON_Msk            (0x1UL << RCC_CSR1_LSECSSON_Pos)       /*!< 0x00000020 */
 #define RCC_CSR1_LSECSSON                RCC_CSR1_LSECSSON_Msk

system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h

@@ -4402,10 +4402,8 @@ typedef struct
 #define RCC_CSR1_LSEBYP_Msk              (0x1UL << RCC_CSR1_LSEBYP_Pos)         /*!< 0x00000004 */
 #define RCC_CSR1_LSEBYP                  RCC_CSR1_LSEBYP_Msk
 #define RCC_CSR1_LSEDRV_Pos              (3U)
-#define RCC_CSR1_LSEDRV_Msk              (0x3UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000018 */
+#define RCC_CSR1_LSEDRV_Msk              (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
 #define RCC_CSR1_LSEDRV                  RCC_CSR1_LSEDRV_Msk
-#define RCC_CSR1_LSEDRV_0                (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
-#define RCC_CSR1_LSEDRV_1                (0x2UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000010 */
 #define RCC_CSR1_LSECSSON_Pos            (5U)
 #define RCC_CSR1_LSECSSON_Msk            (0x1UL << RCC_CSR1_LSECSSON_Pos)       /*!< 0x00000020 */
 #define RCC_CSR1_LSECSSON                RCC_CSR1_LSECSSON_Msk

system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h

@@ -4523,10 +4523,8 @@ typedef struct
 #define RCC_CSR1_LSEBYP_Msk              (0x1UL << RCC_CSR1_LSEBYP_Pos)         /*!< 0x00000004 */
 #define RCC_CSR1_LSEBYP                  RCC_CSR1_LSEBYP_Msk
 #define RCC_CSR1_LSEDRV_Pos              (3U)
-#define RCC_CSR1_LSEDRV_Msk              (0x3UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000018 */
+#define RCC_CSR1_LSEDRV_Msk              (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
 #define RCC_CSR1_LSEDRV                  RCC_CSR1_LSEDRV_Msk
-#define RCC_CSR1_LSEDRV_0                (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
-#define RCC_CSR1_LSEDRV_1                (0x2UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000010 */
 #define RCC_CSR1_LSECSSON_Pos            (5U)
 #define RCC_CSR1_LSECSSON_Msk            (0x1UL << RCC_CSR1_LSECSSON_Pos)       /*!< 0x00000020 */
 #define RCC_CSR1_LSECSSON                RCC_CSR1_LSECSSON_Msk

system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c071xx.h

@@ -4895,10 +4895,8 @@ typedef struct
 #define RCC_CSR1_LSEBYP_Msk              (0x1UL << RCC_CSR1_LSEBYP_Pos)         /*!< 0x00000004 */
 #define RCC_CSR1_LSEBYP                  RCC_CSR1_LSEBYP_Msk
 #define RCC_CSR1_LSEDRV_Pos              (3U)
-#define RCC_CSR1_LSEDRV_Msk              (0x3UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000018 */
+#define RCC_CSR1_LSEDRV_Msk              (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
 #define RCC_CSR1_LSEDRV                  RCC_CSR1_LSEDRV_Msk
-#define RCC_CSR1_LSEDRV_0                (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
-#define RCC_CSR1_LSEDRV_1                (0x2UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000010 */
 #define RCC_CSR1_LSECSSON_Pos            (5U)
 #define RCC_CSR1_LSECSSON_Msk            (0x1UL << RCC_CSR1_LSECSSON_Pos)       /*!< 0x00000020 */
 #define RCC_CSR1_LSECSSON                RCC_CSR1_LSECSSON_Msk

system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c091xx.h

@@ -103,6 +103,8 @@ typedef enum
   USART3_4_IRQn               = 29,     /*!< USART3/4 global interrupt(combined with EXTI 28)                  */
 } IRQn_Type;
 
+/* Legacy define */
+#define DMAMUX1_DMA1_CH4_5_IRQHandler   DMAMUX1_DMA1_CH4_5_6_7_IRQHandler
 /**
   * @}
   */
@@ -4725,10 +4727,8 @@ typedef struct
 #define RCC_CSR1_LSEBYP_Msk              (0x1UL << RCC_CSR1_LSEBYP_Pos)         /*!< 0x00000004 */
 #define RCC_CSR1_LSEBYP                  RCC_CSR1_LSEBYP_Msk
 #define RCC_CSR1_LSEDRV_Pos              (3U)
-#define RCC_CSR1_LSEDRV_Msk              (0x3UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000018 */
+#define RCC_CSR1_LSEDRV_Msk              (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
 #define RCC_CSR1_LSEDRV                  RCC_CSR1_LSEDRV_Msk
-#define RCC_CSR1_LSEDRV_0                (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
-#define RCC_CSR1_LSEDRV_1                (0x2UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000010 */
 #define RCC_CSR1_LSECSSON_Pos            (5U)
 #define RCC_CSR1_LSECSSON_Msk            (0x1UL << RCC_CSR1_LSECSSON_Pos)       /*!< 0x00000020 */
 #define RCC_CSR1_LSECSSON                RCC_CSR1_LSECSSON_Msk

system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c092xx.h

@@ -105,6 +105,8 @@ typedef enum
   FDCAN1_IT1_IRQn             = 31,     /*!< FDCAN1 global Interrupt 1                                         */
 } IRQn_Type;
 
+/* Legacy define */
+#define DMAMUX1_DMA1_CH4_5_IRQHandler   DMAMUX1_DMA1_CH4_5_6_7_IRQHandler
 /**
   * @}
   */
@@ -5389,10 +5391,8 @@ typedef struct
 #define RCC_CSR1_LSEBYP_Msk              (0x1UL << RCC_CSR1_LSEBYP_Pos)         /*!< 0x00000004 */
 #define RCC_CSR1_LSEBYP                  RCC_CSR1_LSEBYP_Msk
 #define RCC_CSR1_LSEDRV_Pos              (3U)
-#define RCC_CSR1_LSEDRV_Msk              (0x3UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000018 */
+#define RCC_CSR1_LSEDRV_Msk              (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
 #define RCC_CSR1_LSEDRV                  RCC_CSR1_LSEDRV_Msk
-#define RCC_CSR1_LSEDRV_0                (0x1UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000008 */
-#define RCC_CSR1_LSEDRV_1                (0x2UL << RCC_CSR1_LSEDRV_Pos)         /*!< 0x00000010 */
 #define RCC_CSR1_LSECSSON_Pos            (5U)
 #define RCC_CSR1_LSECSSON_Msk            (0x1UL << RCC_CSR1_LSECSSON_Pos)       /*!< 0x00000020 */
 #define RCC_CSR1_LSECSSON                RCC_CSR1_LSECSSON_Msk

system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h

@@ -80,11 +80,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.0.0
+  * @brief CMSIS Device version number V1.4.1
   */
 #define __STM32C0_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32C0_CMSIS_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
-#define __STM32C0_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32C0_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
+#define __STM32C0_CMSIS_VERSION_SUB2   (0x01U) /*!< [15:8]  sub2 version */
 #define __STM32C0_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32C0_CMSIS_VERSION        ((__STM32C0_CMSIS_VERSION_MAIN << 24)\
                                        |(__STM32C0_CMSIS_VERSION_SUB1 << 16)\

system/Drivers/CMSIS/Device/ST/STM32C0xx/LICENSE.md

@@ -198,4 +198,4 @@
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
-   limitations under the License.
+   limitations under the License.

system/Drivers/CMSIS/Device/ST/STM32C0xx/README.md

@@ -1,6 +1,6 @@
 # STM32CubeC0 CMSIS Device MCU Component
 
-![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_c0.svg?color=brightgreen)
+![tag](https://img.shields.io/badge/tag-v1.4.1-brightgreen.svg)
 
 ## Overview
 
@@ -33,4 +33,4 @@ The full **STM32CubeC0** MCU package is available [here](https://github.com/STMi
 
 ## Troubleshooting
 
-Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.

system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.html

@@ -5,172 +5,156 @@
   <meta name="generator" content="pandoc" />
   <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
   <title>Release Notes for STM32C0xx CMSIS</title>
-  <style>
-    code{white-space: pre-wrap;}
-    span.smallcaps{font-variant: small-caps;}
-    div.columns{display: flex; gap: min(4vw, 1.5em);}
-    div.column{flex: auto; overflow-x: auto;}
-    div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
-    /* The extra [class] is a hack that increases specificity enough to
-       override a similar rule in reveal.js */
-    ul.task-list[class]{list-style: none;}
-    ul.task-list li input[type="checkbox"] {
-      font-size: inherit;
-      width: 0.8em;
-      margin: 0 0.8em 0.2em -1.6em;
-      vertical-align: middle;
-    }
-    .display.math{display: block; text-align: center; margin: 0.5rem auto;}
+  <style type="text/css">
+      code{white-space: pre-wrap;}
+      span.smallcaps{font-variant: small-caps;}
+      span.underline{text-decoration: underline;}
+      div.column{display: inline-block; vertical-align: top; width: 50%;}
   </style>
   <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
-  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
   <!--[if lt IE 9]>
     <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
   <![endif]-->
+  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
 </head>
 <body>
 <div class="row">
 <div class="col-sm-12 col-lg-4">
 <center>
-<h1 id="release-notes-for-stm32c0xx-cmsis">Release Notes for
-<mark> STM32C0xx CMSIS </mark></h1>
+<h1 id="release-notes-for-stm32c0xx-cmsis">Release Notes for <mark> STM32C0xx CMSIS </mark></h1>
 <p>Copyright © 2022 STMicroelectronics<br />
 </p>
-<a href="https://www.st.com" class="logo"><img
-src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
 </center>
 </div>
-<section id="update-history" class="col-sm-12 col-lg-8">
-<h1><strong>Update History</strong></h1>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history"><strong>Update History</strong></h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section4" checked aria-hidden="true">
-<label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0
-/ 30-October-2024</strong></label>
+<input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" checked aria-hidden="true"><strong>V1.4.1 / 26-June-2026</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
-<li>Official release of STM32C0xx CMSIS drivers to support
-<strong>STM32C051xx</strong> and <strong>STM32C091/92xx</strong>
-devices</li>
 <li>General updates to fix known defects and enhance implementation</li>
-<li>Align version of bit and registers definition with the STM32C0
-reference manual</li>
 </ul>
 <h2 id="contents">Contents</h2>
 <ul>
+<li>Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.</li>
+<li>Fix RCC_CSR1_LSEDRV_Msk definition to match actual field width</li>
+<li>Fix DMAMUX1/DMA1 shared interrupt handler name</li>
+<li>Add IAR linker configuration file for STM32C071x8</li>
+</ul>
+<h2 id="supported-devices">Supported Devices</h2>
+<ul>
+<li>STM32C011xx, STM32C031xx, STM32C051xx, STM32C071xx and STM32C091/92xx devices</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 05-February-2025</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>No CMSIS-related fixes were included in this release.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0 / 30-October-2024</strong></label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
+<li>Official release of STM32C0xx CMSIS drivers to support <strong>STM32C051xx</strong> and <strong>STM32C091/92xx</strong> devices</li>
+<li>General updates to fix known defects and enhance implementation</li>
+<li>Align version of bit and registers definition with the STM32C0 reference manual</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<ul>
 <li><strong>Support of STM32C051xx and STM32C091/92xx devices</strong>:
 <ul>
-<li>Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h”
-files</li>
-<li>Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s”
-and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM
-toolchains</li>
-<li>Add STM32C051xx and STM32C091/92xx devices linker files for EWARM
-and STM32CubeIDE toolchains</li>
+<li>Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h” files</li>
+<li>Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s” and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains</li>
+<li>Add STM32C051xx and STM32C091/92xx devices linker files for EWARM and STM32CubeIDE toolchains</li>
 </ul></li>
 <li><strong>Registers and bit field definitions updates</strong> :
 <ul>
-<li>Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware
-addresses</li>
-<li>Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS
-files as undefined</li>
+<li>Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware addresses</li>
+<li>Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS files as undefined</li>
 </ul></li>
 </ul>
-<h2 id="supported-devices">Supported Devices</h2>
+<h2 id="supported-devices-1">Supported Devices</h2>
 <ul>
-<li>STM32C011xx, STM32C031xx, <strong>STM32C051xx</strong>, STM32C071xx
-and <strong>STM32C091/92xx</strong> devices</li>
+<li>STM32C011xx, STM32C031xx, <strong>STM32C051xx</strong>, STM32C071xx and <strong>STM32C091/92xx</strong> devices</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
-<input type="checkbox" id="collapse-section3" aria-hidden="true">
-<label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 /
-05-June-2024</strong></label>
+<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 05-June-2024</strong></label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <ul>
-<li>First official release of STM32C0xx CMSIS drivers to support
-<strong>STM32C071xx</strong> devices</li>
+<li>First official release of STM32C0xx CMSIS drivers to support <strong>STM32C071xx</strong> devices</li>
 <li>General updates to fix known defects and enhance implementation</li>
-<li>Align version of bit and registers definition with the STM32C0
-reference manual</li>
+<li>Align version of bit and registers definition with the STM32C0 reference manual</li>
 </ul>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
 <ul>
 <li><strong>Support of STM32C071xx devices</strong>:
 <ul>
 <li>Add “stm32c071xx.h” file</li>
-<li>Add startup files “startup_stm32c071xx.s” for EWARM, STM32CubeIDE
-and MDK-ARM toolchains</li>
-<li>Add STM32C071xx devices linker files for EWARM and STM32CubeIDE
-toolchains</li>
+<li>Add startup files “startup_stm32c071xx.s” for EWARM, STM32CubeIDE and MDK-ARM toolchains</li>
+<li>Add STM32C071xx devices linker files for EWARM and STM32CubeIDE toolchains</li>
 </ul></li>
 <li><strong>Registers and bit field definitions updates</strong> :
 <ul>
-<li>Add DMAMUX1_RequestGenerator3_BASE and DMAMUX1_RequestGenerator3
-definitions</li>
-<li>Remove DMA_IFCR_CGIF4, DMA_IFCR_CTCIF4, DMA_IFCR_CHTIF4 and
-DMA_IFCR_CTEIF4 definitions</li>
-<li>Add ADC_AWD2CR_AWD2CH_19, ADC_AWD2CR_AWD2CH_20, ADC_AWD2CR_AWD2CH_21
-and ADC_AWD2CR_AWD2CH_22 bits definitions</li>
-<li>Add ADC_AWD3CR_AWD3CH_19, ADC_AWD3CR_AWD3CH_20,
-ADC_AWD3CR_AWD3CH_21, ADC_AWD3CR_AWD3CH_22 bits definitions</li>
+<li>Add DMAMUX1_RequestGenerator3_BASE and DMAMUX1_RequestGenerator3 definitions</li>
+<li>Remove DMA_IFCR_CGIF4, DMA_IFCR_CTCIF4, DMA_IFCR_CHTIF4 and DMA_IFCR_CTEIF4 definitions</li>
+<li>Add ADC_AWD2CR_AWD2CH_19, ADC_AWD2CR_AWD2CH_20, ADC_AWD2CR_AWD2CH_21 and ADC_AWD2CR_AWD2CH_22 bits definitions</li>
+<li>Add ADC_AWD3CR_AWD3CH_19, ADC_AWD3CR_AWD3CH_20, ADC_AWD3CR_AWD3CH_21, ADC_AWD3CR_AWD3CH_22 bits definitions</li>
 <li>Add FLASH_OPTR_SECURE_MUXING_EN bit definition</li>
 <li>Correct Flash page number section mask (FLASH_CR_PNB_Msk)</li>
 <li>Remove extra FLASH_ECCR register bits definitions</li>
-<li>Correct masks values of FLASH_PCROP1ASR, FLASH_WRP1AR, FLASH_WRP1BR,
-FLASH_WRP1BR, FLASH_PCROP1BER registers</li>
+<li>Correct masks values of FLASH_PCROP1ASR, FLASH_WRP1AR, FLASH_WRP1BR, FLASH_WRP1BR, FLASH_PCROP1BER registers</li>
 <li>Add FLASH_SIZE macro to compute Flash size value</li>
-<li>Fix correct FLASH_OPTR_BORF_LEV and FLASH_OPTR_BORR_LEV
-positions</li>
+<li>Fix correct FLASH_OPTR_BORF_LEV and FLASH_OPTR_BORR_LEV positions</li>
 <li>Remove SYSCFG_CFGR1_BOOSTEN bit definition</li>
 <li>Correct SYSCFG_CFGR3 register bits masks values</li>
-<li>Change SYSCFG_ITLINE0_SR_EWDG bit definition naming by
-SYSCFG_ITLINE0_SR_WWDG to be aligned with the reference manual</li>
-<li>Change SYSCFG_ITLINE4_SR_CLK_CTRL bit definition naming by
-SYSCFG_ITLINE4_SR_RCC to be aligned with the reference manual</li>
+<li>Change SYSCFG_ITLINE0_SR_EWDG bit definition naming by SYSCFG_ITLINE0_SR_WWDG to be aligned with the reference manual</li>
+<li>Change SYSCFG_ITLINE4_SR_CLK_CTRL bit definition naming by SYSCFG_ITLINE4_SR_RCC to be aligned with the reference manual</li>
 <li>Update IS_TIM_REMAP_INSTANCE and IS_TIM_ETRSEL_INSTANCE macros</li>
 <li>Update TIM Capture/Compare masks values</li>
 <li>Remove extra EXTI interrupts and events Masks</li>
 <li>Remove extra PWR_SR2_REGLPF bits definition</li>
 <li>Update some RCC_CFGR bit definitions
 <ul>
-<li>Remove RCC_CFGR_MCO2PRE_3 and RCC_CFGR_MCOPRE_3 bits definitions as
-reserved</li>
-<li>Update RCC_CFGR_MCO2PRE_Msk and RCC_CFGR_MCOPRE_Msk masks
-values</li>
+<li>Remove RCC_CFGR_MCO2PRE_3 and RCC_CFGR_MCOPRE_3 bits definitions as reserved</li>
+<li>Update RCC_CFGR_MCO2PRE_Msk and RCC_CFGR_MCOPRE_Msk masks values</li>
 </ul></li>
 </ul></li>
 </ul>
-<h2 id="supported-devices-1">Supported Devices</h2>
+<h2 id="supported-devices-2">Supported Devices</h2>
 <ul>
 <li>STM32C011xx, STM32C031xx and STM32C071xx devices</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
-<input type="checkbox" id="collapse-section2" aria-hidden="true">
-<label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 /
-07-June-2023</strong></label>
-<h2 id="main-changes-2">Main Changes</h2>
+<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 07-June-2023</strong></label>
+<div>
+<h2 id="main-changes-4">Main Changes</h2>
 <p>Align flash register address with STM32C0 reference manual</p>
 </div>
+</div>
 <div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true">
-<label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 /
-09-February-2022</strong></label>
-<h2 id="main-changes-3">Main Changes</h2>
-<p>First official release version of bits and registers definition
-aligned with STM32C0 reference manual</p>
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 09-February-2022</strong></label>
+<div>
+<h2 id="main-changes-5">Main Changes</h2>
+<p>First official release version of bits and registers definition aligned with STM32C0 reference manual</p>
+</div>
+</div>
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+This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.
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