Auditable prefix-cache capacity curves with compacting Fenwick ranks, exact LRU validation, and reproducible public-trace benchmarks.
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Updated
Sep 26, 2026 - Python
Auditable prefix-cache capacity curves with compacting Fenwick ranks, exact LRU validation, and reproducible public-trace benchmarks.
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Computer Architecture II handouts (UoA DI, Fall 2024). Handout 1: hand-written MIPS pipeline assembly. Handout 2: cache-configuration analysis across three MIPS variants × two programs × four cache sizes via QtMips. Team of two.
Low-level programming and computer architecture research. RISC-V Assembly, Ripes simulations, and hardware-software interaction. Collaboration with Nikita Bulkin (University teammate)
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