WassimHedfi / FPGA-Projects Star 11 Code Issues Pull requests This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera. c fpga vhdl verilog modelsim quartus-prime de10-lite fpga-design programmable-logic-design softcore-processor-design Updated Sep 26, 2024 Verilog
AEjonanonymous / Gardner-Logic-Bridge Star 1 Code Issues Pull requests Rescuing Moore’s Law via Room-Temperature Soliton Integration in Standard Silicon. fpga information-theory javascript-engine systemverilog hardware-designs logic-gates constraint-based-modeling topological-materials inverse-scattering computational-methods moores-law soliton-dynamics independent-time softcore-processor-design room-temperature-superconductors post-cmos soliton-physics threshold-optimization iso-velocity-computation Updated Apr 22, 2026 SystemVerilog
mujahedeenkompakhaitianmonetaryunit765 / Gardner-Logic-Bridge Star 1 Code Issues Pull requests Build a Gardner Logic-Bridge IP core for threshold-programmable, room-temperature soliton logic in standard silicon fpga information-theory javascript-engine systemverilog hardware-designs logic-gates constraint-based-modeling topological-materials inverse-scattering computational-methods moores-law soliton-dynamics independent-time softcore-processor-design room-temperature-superconductors post-cmos soliton-physics threshold-optimization iso-velocity-computation Updated Sep 15, 2026 SystemVerilog
0xArt / Biscuit Star 0 Code Issues Pull requests The lightweight RISCV core. embedded fpga riscv verilog verilog-hdl riscv32 softcore softcore-processor-design Updated Jul 15, 2026 SystemVerilog
mit41301 / PandaBuilder Star 0 Code Issues Pull requests PandaBuilder by Logic Solutions Bründler cpu vhdl systemverilog panda softcore verilo softcore-processor-design Updated Sep 12, 2026 VHDL