Skip to content

Fix fpga chip passing gate's internal table instead of chip entity to output function#3656

Merged
Astralcircle merged 1 commit into
wiremod:masterfrom
Astralcircle:cantool
Jul 17, 2026
Merged

Fix fpga chip passing gate's internal table instead of chip entity to output function#3656
Astralcircle merged 1 commit into
wiremod:masterfrom
Astralcircle:cantool

Conversation

@Astralcircle

Copy link
Copy Markdown
Contributor

Because of this all gates that used WireLib.CanTool did not work in FPGA

… output function

Because of this all gates that used WireLib.CanTool did not work in FPGA
@Astralcircle
Astralcircle merged commit 6fdc26a into wiremod:master Jul 17, 2026
1 check passed
@Astralcircle
Astralcircle deleted the cantool branch July 17, 2026 00:32
@XAYRGA

XAYRGA commented Jul 17, 2026

Copy link
Copy Markdown
Contributor

Might want to revisit this one. This causes gates which use variables on the table to explode.

eg. Timer / Smoother gates set a variable on the gate called "Accum" in their :reset() function.

image

gate.Reset is called on the Gate table, not the entity table, so these values are never initialized.

when .output is called with the entity , it will not have these initial values on the entity table.

image

Furthermore, any fields that the output functions attempt to access will now be shared for the entire FPGA instead of instanced.

Astralcircle added a commit to Astralcircle/wire that referenced this pull request Jul 18, 2026
Astralcircle added a commit that referenced this pull request Jul 18, 2026
* Revert "Fix fpga chip passing gate's internal table instead of chip entity to output function (#3656)"

This reverts commit 6fdc26a.

* Fix entity gates for FPGA by another way

* Remove some useless IsValid checks
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants