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contract: Nars16x8, MoorePalettePairs, MooreNars16 value tenants (ordinals 18-20) - #1408

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Oct 8, 2026
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AdaWorldAPI merged 2 commits into
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ccr-b2e415d9-4jfvyk-tenants

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@AdaWorldAPI AdaWorldAPI commented Oct 8, 2026 •

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Three append-only value tenants after Register1. Layout-preserving: NodeRow stays 512 B, tenants 0..17 and all CE64 fields are unchanged, and there is no ENVELOPE_LAYOUT_VERSION bump. Commits: 28ec7c0 (code and tests), 75c83c4 (docs and board), 0c280e4 (merge of main with #1407), d076a6a (J follows the strict ISA), 7852ed4 (board fix).

Byte table

ord tenant kind row bytes slab bytes
18 Nars16x8 U16 × 8, LE [284,300) [252,268)
19 MoorePalettePairs U8 × 16 [300,316) [268,284)
20 MooreNars16 U16 × 8, LE [316,332) [284,300)

New module contract::moore_tenant

  • MooreSlot, MooreNars16, MooreTenantView and MooreTenantMut. All lane access goes through ValueTenant::value_offset(); there is no literal offset.
  • DirectionReading::require_sign_triple refuses a Moore-local direction.
  • MooreTenantMut::lift_ce64 refuses mixed witnesses and Epi5 codes 24..31. It checks all eight lanes before writing any, and returns the witness to the owner.
  • No truth formula. No CE64 change.

Tests A–L

  • A–E, G–I, K, L: in moore_tenant.rs, 11 tests. G is exhaustive over all 65536 lane values, plus a CE64 bit map.
  • F: cognitive-shader-driver/tests/moore_palette_pairs_lut.rs. Checks the tenant pairs against PairAddress, PaletteLut and Quad8.
  • J: lance-graph-planner/tests/moore_tenant_isa_equivalence.rs. Lifts through the shipped tenant and runs the strict ISA from CE64 ISA: strict decoder, register methods, field contracts #1407: forward and learn in both operand positions, plus syllogize. Fixtures use only the five executable codes. Over 256 tenants × 8 lanes × 5 ops there are 0 divergences outside the sign triple. An anti-vacuity test restores the wrong witness and shows the result diverges.
  • Three existing tests pinned the Full total at 252. They are re-pinned to 300 on purpose.

Disable runs (each one red, then restored)

disable caught by
E/W slot order swapped E, I
u16 lanes big-endian D, I
pair bytes read swapped F
witness check removed I
refused lift writes a lane first I
Moore direction passes as a sign triple H
energy read as 3 bits J (re-verified after the #1407 merge)
ce64_upper drops the witness J
Nars16x8 descriptor changed to U8 × 16 A
Full drops MooreNars16 compile-time assert

Open

  • The Nars16x8 u16 reading is not declared anywhere.
  • No SlabReading variant gates these tenants yet.
  • There is no production reader or writer.

Docs: .claude/v3/soa_layout/tenants.md (rows 16–20), le-contract.md §3c, board entry entries/2026-10-08-hhtl-nars-moore-value-tenants.md.

🤖 Generated with Claude Code

https://claude.ai/code/session_01EFw2WdKr1oxvaKCJC2ua2R

claude added 2 commits October 8, 2026 08:52
Three append-only 16-byte value tenants after Register1:
- Nars16x8 = 18, U16 x 8 at row [284,300)
- MoorePalettePairs = 19, U8 x 16 at row [300,316)
- MooreNars16 = 20, U16 x 8 at row [316,332)

Layout-preserving: NodeRow stays 512, existing tenants and CE64 fields are
unchanged, no ENVELOPE_LAYOUT_VERSION bump. ValueSchema::Full carries all
three; narrower presets do not. The BoardAggregates reservation re-bases
to 21.

moore_tenant.rs adds the canonical slot order (NW,N,NE,W,E,SW,S,SE),
zero-copy lane access through value_offset(), the MooreNars16 reading
(Pearl3|Energy4|Plasticity3|Polarity1|Epi5), the direction refusal for
sign-triple consumers, and a homogeneous-witness lift that refuses mixed W
and reserved Epi5 codes without writing.

Tests A-L: layout, preservation of tenants 0..17, lane isolation, LE
round trip, slot identity, Palette256 pairs vs PairAddress (#1336),
exhaustive field round trip, direction refusal, witness ownership, ISA
observational equivalence through the shipped ops, zero fallback, codec
mutations. Full byte total re-pinned 252 -> 300.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01EFw2WdKr1oxvaKCJC2ua2R
tenants.md gains rows for Register0/1 (shipped without a row) and the
three new tenants; le-contract.md gains section 3c on non-facet Moore
lanes; board entry records the byte table, refusals, tests A-L and the
ten disable runs.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01EFw2WdKr1oxvaKCJC2ua2R
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  • crates/lance-graph-contract/src/canonical_node.rs
  • crates/lance-graph-contract/src/lib.rs
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AdaWorldAPI marked this pull request as ready for review October 8, 2026 08:59
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AdaWorldAPI merged commit a76d9ab into main Oct 8, 2026
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///
/// [`MooreRefusal::ReservedEpi5`] for a code outside the canonical codebook.
pub const fn epistemic(self, slot: MooreSlot) -> Result<EpistemicState5, MooreRefusal> {
match EpistemicState5::decode(Epi5Gen::V1, self.epi5_raw()) {

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P2 Badge Require declared provenance before decoding Epi5

When a lane is lifted from a legacy or otherwise undeclared CE64 source whose bits 59..63 happen to be in 0..23, this direct decode returns a plausible canonical EpistemicState5 instead of refusing it. The decoder itself explicitly says edge reads must go through Epi5Declarations::project_state5, which checks class, rail, generation, and provenance; because lift_ce64 exposes none of that context and calls this method for validation, legacy temporal bits can silently acquire current epistemic semantics. Accept and validate the declaration/provenance during lifting, or keep the field raw until a declared projection is available.

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Comment on lines +338 to +340
fn set_u16(&mut self, tenant: ValueTenant, slot: MooreSlot, v: u16) {
let at = tenant.value_offset() + 2 * slot.index();
self.value[at..at + 2].copy_from_slice(&v.to_le_bytes());

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P2 Badge Record Moore writes in the tenant counters

When the crate is built with tenant-counters, writes through set_nars16, set_moore_nars16, set_palette_pair, and successful lift_ce64 calls never invoke tenant_update, so snapshots report zero activity for all three new tenants even while their bytes are changing. This breaks the documented per-tenant write-cascade instrumentation used by census and wiring measurements; each public setter path should increment its corresponding tenant counter, as the existing Kanban, style-lane, and Register128 setters do.

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