RISC-V: widen the ZVL256B AXPY vector length to LMUL m4

[6eanut]

Summary

Raise the LMUL of the ZVL256B real AXPY kernel from m2 to m4.

With a 256-bit vector unit, m2 moves 16 single-precision (8 double-precision)
elements per vle/vse, so the main loop, whose VL is clamped to VLMAX, runs
ceil(n/16) (resp. ceil(n/8)) times. The register file is 32 vector registers
wide and the kernel keeps four vector operands live (vx0, vx1, vy0, vy1),
so m2 occupies 8 of them — the grouping is narrower than the register budget
needs.

m4 doubles the elements per vector load and store and halves both the loop trip
count and the number of vsetvli executions for the same n. It also matches
the branch this file already takes for the other riscv64 targets, where LMUL is
already m4.

Only the vector register grouping changes: for a given column each element is
still processed by one vfmacc over the same operand triplets in the same
ascending element order, so each y[i] accumulates the same sequence of addends
as before. For non-zero increments the emitted results are bit-identical.

This backs both SAXPY and DAXPY.

Performance

benchmark/saxpy.goto and benchmark/daxpy.goto, one X100 core at 2.2 GHz,
single thread, warm-up once and the median of three runs per size:

Benchmark	Size	Baseline	Patched	Change
saxpy	256	3603.45	4518.35	+25.39%
saxpy	512	4511.64	5801.53	+28.59%
saxpy	1024	5288.00	6882.56	+30.15%
daxpy	256	2168.87	2789.62	+28.62%
daxpy	512	2535.53	3437.93	+35.59%
daxpy	1024	2701.35	3787.78	+40.22%

Testing

• make tests returns 0: 125/125 utests, 1473/1473 extension tests, no new
  CBLAS failure.
• Differential test under QEMU with guard pages around every buffer: 11136
  single-precision and 11136 double-precision cases, covering n = 0..4097 and
  increments of 1, 2, 3, 4, 5, 7, 8 and 16, produce output bit-identical to the
  unpatched kernel, with no out-of-bounds access. Both builds were also checked
  against a double-precision reference.
• The emitted code was disassembled to confirm the change is real: every
  vsetvli in the kernel moves from e32,m2/e64,m2 to e32,m4/e64,m4.