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Tighten the clock period for gt2n designs #4570

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Merged
maliberty merged 1 commit into from
Sep 27, 2026
Merged

Tighten the clock period for gt2n designs #4570

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4 changes: 1 addition & 3 deletions flow/designs/gt2n/aes/constraint.sdc
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Expand Up @@ -2,9 +2,7 @@ current_design aes_cipher_top

set clk_name clk
set clk_port_name clk
# GT2N lib uses time_unit = 1 ps. 500 ps -> 2 GHz target; first-pass
# loose, can tighten once routing is clean.
set clk_period 500
set clk_period 350
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set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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4 changes: 1 addition & 3 deletions flow/designs/gt2n/gcd/constraint.sdc
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Expand Up @@ -2,9 +2,7 @@ current_design gcd

set clk_name core_clock
set clk_port_name clk
# 500 ps clock (2 GHz) — modest target; lib path delays grow once realistic
# wire RC kicks in. Tighten once a clean run lands.
set clk_period 500
set clk_period 170
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set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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5 changes: 1 addition & 4 deletions flow/designs/gt2n/jpeg/constraint.sdc
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Expand Up @@ -2,10 +2,7 @@ current_design jpeg_encoder

set clk_name clk
set clk_port_name clk
# GT2N lib uses time_unit = 1 ps. 1500 ps -> 667 MHz. Loose first-pass
# target with the analytical-RC stand-in -- tighten once the optimize-ppa
# loop has the baseline period_min.
set clk_period 1000
set clk_period 400
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maliberty marked this conversation as resolved.
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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