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Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
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This pull request updates the clock period constraints across multiple designs (including aes-mbff, ibex, mock-cpu, uart-blocks, gcd, jpeg, cva6, and sky130hd) to tighten timing requirements, and corrects the SDC file path for the aes-mbff design. The review feedback highlights that reducing the clock period for the CVA6 design on Nangate45 from 1000 to 1.0 is overly aggressive and likely to cause severe timing violations, suggesting a more realistic value of 10.0 instead.
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🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 9 with regression(s), 0 without a comparable baseline. ❌ asap7/aes-mbff base — 2 failing metric(s)
❌ asap7/ibex base — 4 failing metric(s)
❌ asap7/mock-cpu base — 6 failing metric(s)
❌ gt2n/gcd base — 7 failing metric(s)
❌ gt2n/jpeg base — 4 failing metric(s)
❌ ihp-sg13g2/gcd base — 10 failing metric(s)
❌ ihp-sg13g2/jpeg base — 5 failing metric(s)
❌ nangate45/cva6 base — 5 failing metric(s)
❌ sky130hd/ibex base — 6 failing metric(s)
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maliberty
merged commit Sep 28, 2026
4941691
into
The-OpenROAD-Project:master
10 of 12 checks passed
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