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Tighten the clock period on designs with positive ws #4571

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Merged
maliberty merged 1 commit into from
Sep 28, 2026
+11 −11
Merged

Tighten the clock period on designs with positive ws #4571

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2 changes: 1 addition & 1 deletion flow/designs/asap7/aes-mbff/config.mk
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Expand Up @@ -7,7 +7,7 @@ export DESIGN_NICKNAME = aes-mbff
export SYNTH_SLANG_ARGS += --ignore-timing

export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes-mbff/constraint.sdc

export ABC_AREA = 1

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2 changes: 1 addition & 1 deletion flow/designs/asap7/aes-mbff/constraint.sdc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 380
set clk_period 350

# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
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2 changes: 1 addition & 1 deletion flow/designs/asap7/ibex/constraint.sdc
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@@ -1,6 +1,6 @@
set clk_name core_clock
set clk_port_name clk_i
set clk_period 1000
set clk_period 900
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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4 changes: 2 additions & 2 deletions flow/designs/asap7/mock-cpu/constraint.sdc
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Expand Up @@ -31,8 +31,8 @@ source $::env(SDC_FILE_EXTRA)

set sdc_version 2.0

set clk_period 333
set clk2_period 1000
set clk_period 270
set clk2_period 810

set clk1_name clk
create_clock -name $clk1_name -period $clk_period \
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2 changes: 1 addition & 1 deletion flow/designs/gf180/uart-blocks/constraint.sdc
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@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 6
set clk_period 3.2
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc
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@@ -1,6 +1,6 @@
set clk_name clk
set clk_port_name clk
set clk_period 6
set clk_period 3.2
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/gcd/constraint.sdc
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Expand Up @@ -2,7 +2,7 @@ current_design gcd

set clk_name core_clock
set clk_port_name clk
set clk_period 2.8
set clk_period 1.5
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/jpeg/constraint.sdc
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Expand Up @@ -2,7 +2,7 @@ current_design jpeg_encoder

set clk_name clk
set clk_port_name clk
set clk_period 8.0
set clk_period 4.0
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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2 changes: 1 addition & 1 deletion flow/designs/nangate45/cva6/constraint.sdc
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Expand Up @@ -3,7 +3,7 @@
set clk_name main_clk
set clk_port clk_i
set clk_ports_list [list $clk_port]
set clk_period 1000
set clk_period 1.0
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set input_delay 0.46
set output_delay 0.11
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
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2 changes: 1 addition & 1 deletion flow/designs/sky130hd/ibex/constraint.sdc
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Expand Up @@ -2,7 +2,7 @@ current_design ibex_core

set clk_name core_clock
set clk_port_name clk_i
set clk_period 10.0
set clk_period 8.0
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
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